Antonio J. Ginés

Orcid: 0000-0001-5272-5802

According to our database1, Antonio J. Ginés authored at least 43 papers between 2002 and 2023.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Bibliography

2023
Behavioral Model for High-Speed SAR ADCs With On-Chip References.
IEEE Trans. Very Large Scale Integr. Syst., December, 2023

A Single-Event Latchup setup for high-precision AMS circuits.
Proceedings of the IEEE European Test Symposium, 2023

2022
A methodology for defect detection in analog circuits based on causal feature selection.
Proceedings of the 29th IEEE International Conference on Electronics, Circuits and Systems, 2022

2021
Digital Non-Linearity Calibration for ADCs With Redundancy Using a New LUT Approach.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021

2020
Digital calibration of capacitor mismatch and comparison offset in Split-CDAC SAR ADCs with redundancy.
Proceedings of the 18th IEEE International New Circuits and Systems Conference, 2020

Non-Linear Calibration of Pipeline ADCs using a Histogram-Based Estimation of the Redundant INL.
Proceedings of the 18th IEEE International New Circuits and Systems Conference, 2020

Static linearity BIST for V<sub>cm</sub>-based switching SAR ADCs using a reduced-code measurement technique.
Proceedings of the 18th IEEE International New Circuits and Systems Conference, 2020

Fast Simulation of Non-Linear Circuits using Semi-Analytical Solutions Based on the Matrix Exponential.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

Calibration of Capacitor Mismatch and Static Comparator Offset in SAR ADC with Digital Redundancy.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

On-chip reduced-code static linearity test of V<sub>cm</sub>-based switching SAR ADCs using an incremental analog-to-digital converter.
Proceedings of the IEEE European Test Symposium, 2020

2019
Fast adaptive comparator offset calibration in pipeline ADC with self-repairing thermometer to binary encoder.
Int. J. Circuit Theory Appl., 2019

Mismatch and Offset Calibration in Redundant SAR ADC.
Proceedings of the XXXIV Conference on Design of Circuits and Integrated Systems, 2019

2018
Description of SAR ADCs with Digital Redundancy using a Unified Hardware-Based Approach.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

AMS-RF test quality: Assessing defect severity.
Proceedings of the 24th IEEE International Symposium on On-Line Testing And Robust System Design, 2018

Redundant SAR ADCs with Split-capacitor DAC.
Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018

2017
Fast Background Calibration of Sampling Timing Skew in SHA-Less Pipeline ADCs.
IEEE Trans. Very Large Scale Integr. Syst., 2017

Black-Box Calibration for ADCs With Hard Nonlinear Errors Using a Novel INL-Based Additive Code: A Pipeline ADC Case Study.
IEEE Trans. Circuits Syst. I Regul. Pap., 2017

On the limits of machine learning-based test: A calibrated mixed-signal system case study.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

2016
Linearity test of high-speed high-performance ADCs using a self-testable on-chip generator.
Proceedings of the 21th IEEE European Test Symposium, 2016

A 76nW, 4kS/s 10-bit SAR ADC with offset cancellation for biomedical applications.
Proceedings of the 2016 IEEE Asia Pacific Conference on Circuits and Systems, 2016

2015
Background Digital Calibration of Comparator Offsets in Pipeline ADCs.
IEEE Trans. Very Large Scale Integr. Syst., 2015

An approach to the design of low-jitter differential clock recovery circuits for high performance ADCs.
Proceedings of the IEEE 6th Latin American Symposium on Circuits & Systems, 2015

2014
Closed-loop simulation method for evaluation of static offset in discrete-time comparators.
Proceedings of the 21st IEEE International Conference on Electronics, Circuits and Systems, 2014

INL systematic reduced-test technique for Pipeline ADCs.
Proceedings of the 19th IEEE European Test Symposium, 2014

Sigma-delta testability for pipeline A/D converters.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

2013
Inductor characterization in RF LC-VCOs.
Proceedings of the 4th IEEE Latin American Symposium on Circuits and Systems, 2013

2012
Analysis of steady-state common-mode response in differential LC-VCOs.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

Self-biased input common-mode generation for improving dynamic range and yield in inverter-based filters.
Proceedings of the 19th IEEE International Conference on Electronics, Circuits and Systems, 2012

2011
Blind Adaptive Estimation of Integral Nonlinear Errors in ADCs Using Arbitrary Input Stimulus.
IEEE Trans. Instrum. Meas., 2011

2010
On Chopper Effects in Discrete-Time SigmaDelta Modulators.
IEEE Trans. Circuits Syst. I Regul. Pap., 2010

On-chip biased voltage-controlled oscillator with temperature compensation of the oscillation amplitude for robust I/Q generation.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Power optimization of CMOS programmable gain amplifiers with high dynamic range and common-mode feed-forward circuit.
Proceedings of the 17th IEEE International Conference on Electronics, 2010

2009
A survey on digital background calibration of ADCs.
Proceedings of the 19th European Conference on Circuit Theory and Design, 2009

On-line estimation of the integral non-linear errors in analogue-to-digital converters without histogram evaluation.
Proceedings of the 19th European Conference on Circuit Theory and Design, 2009

2008
A 5GHz wide tuning range LC-VCO in sub-micrometer CMOS technology.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008

A 1.2V 5.14mW quadrature frequency synthesizer in 90nm CMOS technology for 2.4GHz ZigBee applications.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008

2007
Novel swapping technique for background calibration of capacitor mismatching in pipeline ADCS.
Proceedings of the 20th Annual Symposium on Integrated Circuits and Systems Design, 2007

Improved Background Algorithms for Pipeline ADC Full Calibration.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

2006
Statistical analysis of a background correlation-based technique for full calibration of pipeline ADCs.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

2005
Full calibration digital techniques for pipeline ADCs.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

2004
Digital Background Gain Error Correction in Pipeline ADCs.
Proceedings of the 2004 Design, 2004

2003
Digital Background Calibration Technique for Pipeline ADCs with Multi-Bit Stages.
Proceedings of the 16th Annual Symposium on Integrated Circuits and Systems Design, 2003

2002
A Mixed-Signal Design Reuse Methodology Based on Parametric Behavioural Models with Non-Ideal Effects.
Proceedings of the 2002 Design, 2002


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