Adoración Rueda

Orcid: 0000-0003-4564-9359

According to our database1, Adoración Rueda authored at least 116 papers between 1987 and 2019.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Bibliography

2019
Fast adaptive comparator offset calibration in pipeline ADC with self-repairing thermometer to binary encoder.
Int. J. Circuit Theory Appl., 2019

Mismatch and Offset Calibration in Redundant SAR ADC.
Proceedings of the XXXIV Conference on Design of Circuits and Integrated Systems, 2019

2018
Description of SAR ADCs with Digital Redundancy using a Unified Hardware-Based Approach.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Redundant SAR ADCs with Split-capacitor DAC.
Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018

2017
Fast Background Calibration of Sampling Timing Skew in SHA-Less Pipeline ADCs.
IEEE Trans. Very Large Scale Integr. Syst., 2017

Black-Box Calibration for ADCs With Hard Nonlinear Errors Using a Novel INL-Based Additive Code: A Pipeline ADC Case Study.
IEEE Trans. Circuits Syst. I Regul. Pap., 2017

On the limits of machine learning-based test: A calibrated mixed-signal system case study.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

2016
Cell-culture measurements using voltage oscillations.
Proceedings of the IEEE 7th Latin American Symposium on Circuits & Systems, 2016

Linearity test of high-speed high-performance ADCs using a self-testable on-chip generator.
Proceedings of the 21th IEEE European Test Symposium, 2016

2015
Background Digital Calibration of Comparator Offsets in Pipeline ADCs.
IEEE Trans. Very Large Scale Integr. Syst., 2015

The Bio-Oscillator: A Circuit for Cell-Culture Assays.
IEEE Trans. Circuits Syst. II Express Briefs, 2015

An approach to the design of low-jitter differential clock recovery circuits for high performance ADCs.
Proceedings of the IEEE 6th Latin American Symposium on Circuits & Systems, 2015

From voltage oscillations to tissue-impedance measurements.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2015

2014
Closed-loop simulation method for evaluation of static offset in discrete-time comparators.
Proceedings of the 21st IEEE International Conference on Electronics, Circuits and Systems, 2014

INL systematic reduced-test technique for Pipeline ADCs.
Proceedings of the 19th IEEE European Test Symposium, 2014

2013
Analysis of process variations' impact on a 2.4 GHz 90 nm CMOS LNA.
Proceedings of the 4th IEEE Latin American Symposium on Circuits and Systems, 2013

Inductor characterization in RF LC-VCOs.
Proceedings of the 4th IEEE Latin American Symposium on Circuits and Systems, 2013

Sinusoidal signal generation for mixed-signal BIST using a harmonic-cancellation technique.
Proceedings of the 4th IEEE Latin American Symposium on Circuits and Systems, 2013

2012
Analysis of steady-state common-mode response in differential LC-VCOs.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

Self-biased input common-mode generation for improving dynamic range and yield in inverter-based filters.
Proceedings of the 19th IEEE International Conference on Electronics, Circuits and Systems, 2012

2011
Blind Adaptive Estimation of Integral Nonlinear Errors in ADCs Using Arbitrary Input Stimulus.
IEEE Trans. Instrum. Meas., 2011

Analog Sinewave Signal Generators for Mixed-Signal Built-in Test Applications.
J. Electron. Test., 2011

Alternate Test of LNAs Through Ensemble Learning of On-Chip Digital Envelope Signatures.
J. Electron. Test., 2011

A 3.6mW @ 1.2V high linear 8<sup>th</sup>-order CMOS complex filter for IEEE 802.15.4 standard.
Proceedings of the 37th European Solid-State Circuits Conference, 2011

2.4-GHz single-ended input low-power low-voltage active front-end for ZigBee applications in 90 nm CMOS.
Proceedings of the 20th European Conference on Circuit Theory and Design, 2011

Improving the Accuracy of RF Alternate Test Using Multi-VDD Conditions: Application to Envelope-Based Test of LNAs.
Proceedings of the 20th IEEE Asian Test Symposium, 2011

2010
On Chopper Effects in Discrete-Time SigmaDelta Modulators.
IEEE Trans. Circuits Syst. I Regul. Pap., 2010

Design of a CMOS closed-loop system with applications to bio-impedance measurements.
Microelectron. J., 2010

A BIST Solution for Frequency Domain Characterization of Analog Circuits.
J. Electron. Test., 2010

On-chip biased voltage-controlled oscillator with temperature compensation of the oscillation amplitude for robust I/Q generation.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Power optimization of CMOS programmable gain amplifiers with high dynamic range and common-mode feed-forward circuit.
Proceedings of the 17th IEEE International Conference on Electronics, 2010

Low-cost signature test of RF blocks based on envelope response analysis.
Proceedings of the 15th European Test Symposium, 2010

(Some) Open Problems to Incorporate BIST in Complex Heterogeneous Integrated Systems.
Proceedings of the Fifth IEEE International Symposium on Electronic Design, 2010

A low power low voltage mixer for 2.4GHz applications in CMOS-90nm technology.
Proceedings of the 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2010

2009
Low-Cost Digital Detection of Parametric Faults in Cascaded SigmaDelta Modulators.
IEEE Trans. Circuits Syst. I Regul. Pap., 2009

Design of A CMOS closed-loop system useful for bio-impedance measurements.
Proceedings of the 16th IEEE International Conference on Electronics, 2009

A survey on digital background calibration of ADCs.
Proceedings of the 19th European Conference on Circuit Theory and Design, 2009

On-line estimation of the integral non-linear errors in analogue-to-digital converters without histogram evaluation.
Proceedings of the 19th European Conference on Circuit Theory and Design, 2009

A CMOS bio-impedance measurement system.
Proceedings of the 2009 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2009

A BIST Solution for the Functional Characterization of RF Systems Based on Envelope Response Analysis.
Proceedings of the Eighteentgh Asian Test Symposium, 2009

2008
Simple Evaluation of the Nonlinearity Signature of an ADC Using a Spectral Approach.
VLSI Design, 2008

A 2.4GHz LNA in a 90-nm CMOS technology designed with ACM model.
Proceedings of the 21st Annual Symposium on Integrated Circuits and Systems Design, 2008

Practical Implementation of a Network Analyzer for Analog BIST Applications.
Proceedings of the Design, Automation and Test in Europe, 2008

A 5GHz wide tuning range LC-VCO in sub-micrometer CMOS technology.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008

A 1.2V 5.14mW quadrature frequency synthesizer in 90nm CMOS technology for 2.4GHz ZigBee applications.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008

2007
Novel swapping technique for background calibration of capacitor mismatching in pipeline ADCS.
Proceedings of the 20th Annual Symposium on Integrated Circuits and Systems Design, 2007

Improved Background Algorithms for Pipeline ADC Full Calibration.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

2006
Statistical analysis of a background correlation-based technique for full calibration of pipeline ADCs.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Experimental Validation of a Fully Digital BISTfor Cascaded Sigma Delta Modulators.
Proceedings of the 11th European Test Symposium, 2006

A Sinewave Analyzer for Mixed-Signal BIST Applications in a 0.35µm Technology.
Proceedings of the 9th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2006), 2006

2005
A tissue impedance measurement chip for myocardial ischemia detection.
IEEE Trans. Circuits Syst. I Regul. Pap., 2005

Sine-Wave Signal Characterization Using Square-Wave and SigmaDelta-Modulation: Application to Mixed-Signal BIST.
J. Electron. Test., 2005

Guest Editorial.
J. Electron. Test., 2005

Full calibration digital techniques for pipeline ADCs.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

2004
Impact of random channel mismatch on the SNR and SFDR of time-interleaved ADCs.
IEEE Trans. Circuits Syst. I Regul. Pap., 2004

A 1-V micropower log-domain integrator based on FGMOS transistors operating in weak inversion.
IEEE J. Solid State Circuits, 2004

A 1.25-V micropower Gm-C filter based on FGMOS transistors operating in weak inversion.
IEEE J. Solid State Circuits, 2004

A Method for Parameter Extraction of Analog Sine-Wave Signals for Mixed-Signal Built-In-Self-Test Applications.
Proceedings of the 2004 Design, 2004

A Digital Test for First-Order [Sigma-Delta] Modulators.
Proceedings of the 2004 Design, 2004

Digital Background Gain Error Correction in Pipeline ADCs.
Proceedings of the 2004 Design, 2004

2003
Oscillation-based test in bandpass oversampled A/D converters.
Microelectron. J., 2003

A Charge Correction Cell for FGMOS-Based Circuits.
Proceedings of the 16th Annual Symposium on Integrated Circuits and Systems Design, 2003

Digital Background Calibration Technique for Pipeline ADCs with Multi-Bit Stages.
Proceedings of the 16th Annual Symposium on Integrated Circuits and Systems Design, 2003

2002
Testing Mixed-Signal Cores: A Practical Oscillation-Based Test in an Analog Macrocell.
IEEE Des. Test Comput., 2002

Practical Oscillation-Based Test of Integrated Filters.
IEEE Des. Test Comput., 2002

Practical Solutions for the Application of the Oscillation-Based-Test: Start-Up and On-Chip Evaluation.
Proceedings of the 20th IEEE VLSI Test Symposium (VTS 2002), Without Testing It's a Gamble, 28 April, 2002

A Continuous-Time Incremental Analog to Digital Converter.
Proceedings of the 15th Annual Symposium on Integrated Circuits and Systems Design, 2002

Low-cost on-chip measurements for Oscillation-Based-Test in Analog Integrated Circuits.
Proceedings of the 3rd Latin American Test Workshop, 2002

Practical solutions for the application of the oscillation-based-test in analog integrated circuits.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

A micropower log domain FGMOS filter.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

High-speed low-power logic gates using floating gates.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

Design of a switched opamp-based bandpass filter in a 0.35 μm CMOS technology.
Proceedings of the 2002 9th IEEE International Conference on Electronics, 2002

Threshold-logic-based design of compressors.
Proceedings of the 2002 9th IEEE International Conference on Electronics, 2002

Practical Oscillation-Based Test in Analog Integrated Filters: Experimental Results.
Proceedings of the 1st IEEE International Workshop on Electronic Design, 2002

A Mixed-Signal Design Reuse Methodology Based on Parametric Behavioural Models with Non-Ideal Effects.
Proceedings of the 2002 Design, 2002

2001
A Low-Voltage Floating-Gate MOS Biquad.
VLSI Design, 2001

New BIST Schemes for Structural Testing of Pipelined Analog to Digital Converters.
J. Electron. Test., 2001

Self-Testable Pipelined ADC with Low Hardware Overhead.
Proceedings of the 19th IEEE VLSI Test Symposium (VTS 2001), Test and Diagnosis in a Nanometric World, 29 April, 2001

A 1.25 V FGMOS filter using translinear circuits.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

Structural testing of pipelined analog to digital converters.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

A 1.5 V 23 MHz low power FGMOS filter.
Proceedings of the 2001 8th IEEE International Conference on Electronics, 2001

Design of a CMOS fully differential switched-opamp for SC circuits at very low power supply voltages.
Proceedings of the 2001 8th IEEE International Conference on Electronics, 2001

Analog/mixed-signal IP modeling for design reuse.
Proceedings of the Conference on Design, Automation and Test in Europe, 2001

2000
νMOS-based Sorter for Arithmetic Applications.
VLSI Design, 2000

Built-In Self-Test in Mixed-Signal ICs: A DTMF Macrocell.
Proceedings of the 13th International Conference on VLSI Design (VLSI Design 2000), 2000

Efficient νMOS Realization of Threshold Voters for Self-Purging Redundancy.
Proceedings of the 13th Annual Symposium on Integrated Circuits and Systems Design, 2000

An Application of Self-Timed Circuits to the Reduction of Switching Noise in Analog-Digital Circuits.
Proceedings of the Integrated Circuit Design, 2000

Alternative DFT Strategies for High-Speed Pipelined Data Converters.
Proceedings of the 1st Latin American Test Workshop, 2000

A g<sub>m</sub>-C floating-gate MOS integrator.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

A low-voltage √x floating-gate MOS integrator.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

VHDL-based behavioural description of pipeline ADCs.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

A Vhdl-Based Methodology for Design and Verification of Pipeline A/D Converters.
Proceedings of the 2000 Design, 2000

1999
Effective oscillation-based test for application to a DTMF filter bank.
Proceedings of the Proceedings IEEE International Test Conference 1999, 1999

Programmable low-voltage continuous-time filter for audio applications.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

vMOS-based sorters for multiplier implementations.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

1998
A high-Q bandpass fully differential SC filter with enhanced testability.
IEEE J. Solid State Circuits, 1998

DfT and on-line test of high-performance data converters: a practical case.
Proceedings of the Proceedings IEEE International Test Conference 1998, 1998

CMOS pipelined A/D converters with concurrent error detection capability.
Proceedings of the 5th IEEE International Conference on Electronics, Circuits and Systems, 1998

An Approach to Realistic Fault Prediction and Layout Design for Testability in Analog Circuits.
Proceedings of the 1998 Design, 1998

Switch-Level Fault Coverage Analysis for Switched-Capacitor Systems.
Proceedings of the 1998 Design, 1998

1997
A DFT Technique for Analog-to-Digital Converters with digital correction.
Proceedings of the 15th IEEE VLSI Test Symposium (VTS'97), 1997

Analog and Mixed-Signal Benchmark Circuits-First Release.
Proceedings of the Proceedings IEEE International Test Conference 1997, 1997

A performance-driven placement algorithm with simultaneous Place&Route optimization for analog ICs.
Proceedings of the European Design and Test Conference, 1997

SWITTEST: Automatic Switch-Level Fault Simulation and Test Evaluation of Switched-Capacitor Systems.
Proceedings of the 34st Conference on Design Automation, 1997

1996
Reducing the impact of DFT on the performance of analog integrated circuits: improved sw-op amp design.
Proceedings of the 14th IEEE VLSI Test Symposium (VTS'96), April 28, 1996

1995
A solution for the on-line test of analog ladder filters.
Proceedings of the 13th IEEE VLSI Test Symposium (VTS'95), April 30, 1995

Statistical behavioral modeling and characterization of A/D converters.
Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, 1995

1994
Programmable switched-current wave analog filters.
IEEE J. Solid State Circuits, August, 1994

A new strategy for testing analog filters.
Proceedings of the 12th IEEE VLSI Test Symposium (VTS'94), 1994

A Study of the Sensitivity of Switched-Current Wave Analog Filters to Mismatching and Clock-Feedthrough Errors.
Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994

A Low-Cost Strategy for Testing Analog Filters.
Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994

An Algorithm for the Place-and-Route Problem in the Layout of Analog Circuits.
Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994

1993
Improving the testability of switched-capacitor filters.
J. Electron. Test., 1993

1992
Testability in analogue cellular neural networks.
Int. J. Circuit Theory Appl., 1992

On-line testing of switched-capacitor filters.
Proceedings of the 10th IEEE VLSI Test Symposium (VTS'92), 1992

1987
Chaos from switched-capacitor circuits: Discrete maps.
Proc. IEEE, 1987


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