Manuel J. Barragan Asian
Orcid: 0000-0003-0187-604X
According to our database1,
Manuel J. Barragan Asian
authored at least 78 papers
between 2005 and 2023.
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Bibliography
2023
Corrections to "Design-Oriented All-Regime All-Region 7-Parameter Short-Channel MOSFET Model Based on Inversion Charge".
IEEE Access, 2023
Proceedings of the 21st IEEE Interregional NEWCAS Conference, 2023
A sub-picosecond resolution jitter instrument for GHz frequencies based on a sub-sampling TDA.
Proceedings of the 21st IEEE Interregional NEWCAS Conference, 2023
Special Session: A high-frequency sinusoidal signal generation using harmonic cancellation.
Proceedings of the 24th IEEE Latin American Test Symposium, 2023
Special Session: On-chip jitter BIST with sub-picosecond resolution at GHz frequencies.
Proceedings of the 24th IEEE Latin American Test Symposium, 2023
Proceedings of the 14th IEEE Latin America Symposium on Circuits and System, 2023
A harmonic cancellation-based high-frequency on-chip sinusoidal signal generator with calibration using a coarse-fine delay cell.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023
Resistive Feedback LNA design using a 7-parameter design-oriented model for advanced technologies.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023
Performance benchmark of State-of-the-art Sub-6-GHz wideband LNAs Based on an Extensive Survey.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023
A wideband sub-6GHz continuously tunable gm-boosted CG Low Noise Amplifier in 28 nm FD-SOI CMOS technology.
Proceedings of the 49th IEEE European Solid State Circuits Conference, 2023
2022
Dataset, October, 2022
Design-Oriented All-Regime All-Region 7-Parameter Short-Channel MOSFET Model Based on Inversion Charge.
IEEE Access, 2022
Proceedings of the 40th IEEE VLSI Test Symposium, 2022
A self-referenced on-chip jitter BIST with sub-picosecond resolution in 28 nm FD-SOI technology.
Proceedings of the 30th IFIP/IEEE 30th International Conference on Very Large Scale Integration, 2022
N-Path Mixer with Wide Rejection Including the 7<sup>th</sup> Harmonic for Low Power Multi-standard Receivers.
Proceedings of the 20th IEEE Interregional NEWCAS Conference, 2022
A methodology for defect detection in analog circuits based on causal feature selection.
Proceedings of the 29th IEEE International Conference on Electronics, Circuits and Systems, 2022
On-chip calibration for high-speed harmonic cancellation-based sinusoidal signal generators.
Proceedings of the IEEE 31st Asian Test Symposium, 2022
2021
IEEE Trans. Circuits Syst. I Regul. Pap., 2021
IEEE Trans. Circuits Syst. I Regul. Pap., 2021
Proceedings of the 19th IEEE International New Circuits and Systems Conference, 2021
Integrated Wideband Millimeter-Wave Bias-Tee - Application to Distributed Amplifier Biasing.
Proceedings of the 19th IEEE International New Circuits and Systems Conference, 2021
Proceedings of the 28th IEEE International Conference on Electronics, 2021
Analysis and mitigation of timing inaccuracies in high-frequency on-chip sinusoidal signal generators based on harmonic cancellation.
Proceedings of the 26th IEEE European Test Symposium, 2021
2020
IEEE Trans. Circuits Syst. I Regul. Pap., 2020
mm-Wave Through-Load Switch for in-situ Vector Network Analyzer on a 55-nm BiCMOS Technology.
Proceedings of the 18th IEEE International New Circuits and Systems Conference, 2020
Static linearity BIST for V<sub>cm</sub>-based switching SAR ADCs using a reduced-code measurement technique.
Proceedings of the 18th IEEE International New Circuits and Systems Conference, 2020
A Comprehensive End-to-end Solution for a Secure and Dynamic Mixed-signal 1687 System.
Proceedings of the 26th IEEE International Symposium on On-Line Testing and Robust System Design, 2020
On-chip reduced-code static linearity test of V<sub>cm</sub>-based switching SAR ADCs using an incremental analog-to-digital converter.
Proceedings of the IEEE European Test Symposium, 2020
2019
Fully Differential 4-V Output Range 14.5-ENOB Stepwise Ramp Stimulus Generator for On-Chip Static Linearity Test of ADCs.
IEEE Trans. Very Large Scale Integr. Syst., 2019
Proceedings of the 27th IFIP/IEEE International Conference on Very Large Scale Integration, 2019
Efficient generation of data sets for one-shot statistical calibration of RF/mm-wave circuits.
Proceedings of the 16th International Conference on Synthesis, 2019
Feature selection and feature design for machine learning indirect test: a tutorial review.
Proceedings of the 16th International Conference on Synthesis, 2019
Yield Recovery of mm-Wave Power Amplifiers using Variable Decoupling Cells and One-Shot Statistical Calibration.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
A 52 dB-SFDR 166 MHz sinusoidal signal generator for mixed-signal BIST applications in 28 nm FDSOI technology.
Proceedings of the 24th IEEE European Test Symposium, 2019
On the use of causal feature selection in the context of machine-learning indirect test.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019
2018
Practical Harmonic Cancellation Techniques for the On-Chip Implementation of Sinusoidal Signal Generators for Mixed-Signal BIST Applications.
J. Electron. Test., 2018
J. Electron. Test., 2018
Proceedings of the 36th IEEE VLSI Test Symposium, 2018
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
Reduced-code static linearity test of SAR ADCs using a built-in incremental ∑Δ converter.
Proceedings of the 24th IEEE International Symposium on On-Line Testing And Robust System Design, 2018
Assisted test design for non-intrusive machine learning indirect test of millimeter-wave circuits.
Proceedings of the 23rd IEEE European Test Symposium, 2018
2017
Analysis of an efficient on-chip servo-loop technique for reduced-code static linearity test of pipeline ADCs.
Proceedings of the 35th IEEE VLSI Test Symposium, 2017
Proceedings of the 22nd IEEE European Test Symposium, 2017
Design of a sinusoidal signal generator with calibrated harmonic cancellation for mixed-signal BIST in a 28 nm FDSOI technology.
Proceedings of the 22nd IEEE European Test Symposium, 2017
On the limits of machine learning-based test: A calibrated mixed-signal system case study.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017
2016
A Fully-Digital BIST Wrapper Based on Ternary Test Stimuli for the Dynamic Test of a 40 nm CMOS 18-bit Stereo Audio ΣΔ ADC.
IEEE Trans. Circuits Syst. I Regul. Pap., 2016
Brownian distance correlation-directed search: A fast feature selection technique for alternate test.
Integr., 2016
A 65nm CMOS Ramp Generator Design and its Application Towards a BIST Implementation of the Reduced-Code Static Linearity Test Technique for Pipeline ADCs.
J. Electron. Test., 2016
IEEE Des. Test, 2016
Questioning the reliability of Monte Carlo simulation for machine learning test validation.
Proceedings of the 21th IEEE European Test Symposium, 2016
Linearity test of high-speed high-performance ADCs using a self-testable on-chip generator.
Proceedings of the 21th IEEE European Test Symposium, 2016
2015
Proceedings of the 33rd IEEE VLSI Test Symposium, 2015
Evaluation of low-cost mixed-signal test techniques for circuits with long simulation times.
Proceedings of the 2015 IEEE International Test Conference, 2015
Feature selection for alternate test using wrappers: application to an RF LNA case study.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015
2014
Proceedings of the VLSI-SoC: Internet of Things Foundations, 2014
Proceedings of the 22nd International Conference on Very Large Scale Integration, 2014
On-Chip Implementation of an Integrator-Based Servo-Loop for ADC Static Linearity Test.
Proceedings of the 23rd IEEE Asian Test Symposium, 2014
2013
Sinusoidal signal generation for mixed-signal BIST using a harmonic-cancellation technique.
Proceedings of the 4th IEEE Latin American Symposium on Circuits and Systems, 2013
Proceedings of the 18th IEEE European Test Symposium, 2013
2012
Low-Power Die-Level Process Variation and Temperature Monitors for Yield Analysis and Optimization in Deep-Submicron CMOS.
IEEE Trans. Instrum. Meas., 2012
J. Low Power Electron., 2012
Proceedings of the 13th Latin American Test Workshop, 2012
Proceedings of the 17th IEEE European Test Symposium, 2012
2011
J. Electron. Test., 2011
Alternate Test of LNAs Through Ensemble Learning of On-Chip Digital Envelope Signatures.
J. Electron. Test., 2011
Improving the Accuracy of RF Alternate Test Using Multi-VDD Conditions: Application to Envelope-Based Test of LNAs.
Proceedings of the 20th IEEE Asian Test Symposium, 2011
2010
J. Electron. Test., 2010
On-chip biased voltage-controlled oscillator with temperature compensation of the oscillation amplitude for robust I/Q generation.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
Proceedings of the 15th European Test Symposium, 2010
(Some) Open Problems to Incorporate BIST in Complex Heterogeneous Integrated Systems.
Proceedings of the Fifth IEEE International Symposium on Electronic Design, 2010
2009
A BIST Solution for the Functional Characterization of RF Systems Based on Envelope Response Analysis.
Proceedings of the Eighteentgh Asian Test Symposium, 2009
2008
Proceedings of the Design, Automation and Test in Europe, 2008
2007
Interactive presentation: BIST method for die-level process parameter variation monitoring in analog/mixed-signal integrated circuits.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007
2006
Proceedings of the 9th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2006), 2006
2005
Sine-Wave Signal Characterization Using Square-Wave and SigmaDelta-Modulation: Application to Mixed-Signal BIST.
J. Electron. Test., 2005