Eduardo J. Peralías
Orcid: 0000-0003-0629-0785Affiliations:
- University of Seville, Spain
According to our database1,
Eduardo J. Peralías
authored at least 64 papers
between 1995 and 2023.
Collaborative distances:
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Bibliography
2023
IEEE Trans. Very Large Scale Integr. Syst., December, 2023
Proceedings of the IEEE European Test Symposium, 2023
2021
IEEE Trans. Circuits Syst. I Regul. Pap., 2021
2020
Normalized Nonlinear Semiempirical MOST Model Used in Monolithic RF Class A-to-C PAs.
Circuits Syst. Signal Process., 2020
Digital calibration of capacitor mismatch and comparison offset in Split-CDAC SAR ADCs with redundancy.
Proceedings of the 18th IEEE International New Circuits and Systems Conference, 2020
Non-Linear Calibration of Pipeline ADCs using a Histogram-Based Estimation of the Redundant INL.
Proceedings of the 18th IEEE International New Circuits and Systems Conference, 2020
Fast Simulation of Non-Linear Circuits using Semi-Analytical Solutions Based on the Matrix Exponential.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
Calibration of Capacitor Mismatch and Static Comparator Offset in SAR ADC with Digital Redundancy.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
2019
Fast adaptive comparator offset calibration in pipeline ADC with self-repairing thermometer to binary encoder.
Int. J. Circuit Theory Appl., 2019
Proceedings of the XXXIV Conference on Design of Circuits and Integrated Systems, 2019
2018
Description of SAR ADCs with Digital Redundancy using a Unified Hardware-Based Approach.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018
2017
IEEE Trans. Very Large Scale Integr. Syst., 2017
Black-Box Calibration for ADCs With Hard Nonlinear Errors Using a Novel INL-Based Additive Code: A Pipeline ADC Case Study.
IEEE Trans. Circuits Syst. I Regul. Pap., 2017
On the limits of machine learning-based test: A calibrated mixed-signal system case study.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017
2016
Semi-empirical RF MOST model for CMOS 65 nm technologies: Theory, extraction method and validation.
Integr., 2016
Linearity test of high-speed high-performance ADCs using a self-testable on-chip generator.
Proceedings of the 21th IEEE European Test Symposium, 2016
2015
IEEE Trans. Very Large Scale Integr. Syst., 2015
An approach to the design of low-jitter differential clock recovery circuits for high performance ADCs.
Proceedings of the IEEE 6th Latin American Symposium on Circuits & Systems, 2015
2014
Closed-loop simulation method for evaluation of static offset in discrete-time comparators.
Proceedings of the 21st IEEE International Conference on Electronics, Circuits and Systems, 2014
Proceedings of the 19th IEEE European Test Symposium, 2014
2012
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
Self-biased input common-mode generation for improving dynamic range and yield in inverter-based filters.
Proceedings of the 19th IEEE International Conference on Electronics, Circuits and Systems, 2012
2011
Blind Adaptive Estimation of Integral Nonlinear Errors in ADCs Using Arbitrary Input Stimulus.
IEEE Trans. Instrum. Meas., 2011
A 3.6mW @ 1.2V high linear 8<sup>th</sup>-order CMOS complex filter for IEEE 802.15.4 standard.
Proceedings of the 37th European Solid-State Circuits Conference, 2011
2.4-GHz single-ended input low-power low-voltage active front-end for ZigBee applications in 90 nm CMOS.
Proceedings of the 20th European Conference on Circuit Theory and Design, 2011
2010
IEEE Trans. Circuits Syst. I Regul. Pap., 2010
J. Electron. Test., 2010
On-chip biased voltage-controlled oscillator with temperature compensation of the oscillation amplitude for robust I/Q generation.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
Power optimization of CMOS programmable gain amplifiers with high dynamic range and common-mode feed-forward circuit.
Proceedings of the 17th IEEE International Conference on Electronics, 2010
A fully differential monolithic 2.4GHZ PA for IEEE 802.15.4 based on efficiency design flow.
Proceedings of the 17th IEEE International Conference on Electronics, 2010
2009
Phase noise - consumption trade-off in low power RF-LC-VCO design in micro and nanometric technologies.
Proceedings of the 22st Annual Symposium on Integrated Circuits and Systems Design: Chip on the Dunes, 2009
Proceedings of the 19th European Conference on Circuit Theory and Design, 2009
On-line estimation of the integral non-linear errors in analogue-to-digital converters without histogram evaluation.
Proceedings of the 19th European Conference on Circuit Theory and Design, 2009
2008
VLSI Design, 2008
Proceedings of the 21st Annual Symposium on Integrated Circuits and Systems Design, 2008
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008
A 1.2V 5.14mW quadrature frequency synthesizer in 90nm CMOS technology for 2.4GHz ZigBee applications.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008
2007
Novel swapping technique for background calibration of capacitor mismatching in pipeline ADCS.
Proceedings of the 20th Annual Symposium on Integrated Circuits and Systems Design, 2007
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007
2006
Statistical analysis of a background correlation-based technique for full calibration of pipeline ADCs.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
2005
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
Proceedings of the 12th IEEE International Conference on Electronics, 2005
2004
IEEE Trans. Circuits Syst. I Regul. Pap., 2004
Proceedings of the 2004 Design, 2004
2003
Proceedings of the 16th Annual Symposium on Integrated Circuits and Systems Design, 2003
2002
Testing Mixed-Signal Cores: A Practical Oscillation-Based Test in an Analog Macrocell.
IEEE Des. Test Comput., 2002
A Mixed-Signal Design Reuse Methodology Based on Parametric Behavioural Models with Non-Ideal Effects.
Proceedings of the 2002 Design, 2002
2001
J. Electron. Test., 2001
Proceedings of the 19th IEEE VLSI Test Symposium (VTS 2001), Test and Diagnosis in a Nanometric World, 29 April, 2001
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001
Proceedings of the Conference on Design, Automation and Test in Europe, 2001
2000
An Application of Self-Timed Circuits to the Reduction of Switching Noise in Analog-Digital Circuits.
Proceedings of the Integrated Circuit Design, 2000
Alternative DFT Strategies for High-Speed Pipelined Data Converters.
Proceedings of the 1st Latin American Test Workshop, 2000
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000
Proceedings of the 2000 Design, 2000
1998
IEEE J. Solid State Circuits, 1998
Proceedings of the Proceedings IEEE International Test Conference 1998, 1998
Proceedings of the 5th IEEE International Conference on Electronics, Circuits and Systems, 1998
An Approach to Realistic Fault Prediction and Layout Design for Testability in Analog Circuits.
Proceedings of the 1998 Design, 1998
1997
Proceedings of the 15th IEEE VLSI Test Symposium (VTS'97), 1997
SWITTEST: Automatic Switch-Level Fault Simulation and Test Evaluation of Switched-Capacitor Systems.
Proceedings of the 34st Conference on Design Automation, 1997
1995
Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, 1995