Mohammad Ansari

Orcid: 0000-0002-0965-9667

According to our database1, Mohammad Ansari authored at least 20 papers between 2008 and 2022.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Bibliography

2022
Simple Streaming Algorithms for Edge Coloring.
Proceedings of the 30th Annual European Symposium on Algorithms, 2022

2019
OCTAN: An On-Chip Training Algorithm for Memristive Neuromorphic Circuits.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019

2018
PHAX: Physical Characteristics Aware Ex-Situ Training Framework for Inverter-Based Memristive Neuromorphic Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

An Ultra Low-Power Memristive Neuromorphic Circuit for Internet of Things Smart Sensors.
IEEE Internet Things J., 2018

2016
Purge-Rehab: Eager Software Transactional Memory with High Performance Under Contention.
Int. J. Parallel Program., 2016

2015
A near-threshold 7T SRAM cell with high write and read margins and low write time for sub-20 nm FinFET technologies.
Integr., 2015

2014
Weighted adaptive concurrency control for software transactional memory.
J. Supercomput., 2014

2013
Design of an ultra-low power 32-bit adder operating at subthreshold voltages in 45-nm FinFET.
Proceedings of the 8th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2013

2011
Transaction Reordering to Reduce Aborts in Software Transactional Memory.
Trans. High Perform. Embed. Archit. Compil., 2011

Robust Adaptation to Available Parallelism in Transactional Memory Applications.
Trans. High Perform. Embed. Archit. Compil., 2011

2010
Clustering JVMs with software transactional memory support.
Proceedings of the 24th IEEE International Symposium on Parallel and Distributed Processing, 2010

Improving Performance by Reducing Aborts in Hardware Transactional Memory.
Proceedings of the High Performance Embedded Architectures and Compilers, 2010

2009
Profiling Transactional Memory Applications.
Proceedings of the 17th Euromicro International Conference on Parallel, 2009

On the Performance of Contention Managers for Complex Transactional Memory Benchmarks.
Proceedings of the Eighth International Symposium on Parallel and Distributed Computing, 2009

Steal-on-Abort: Improving Transactional Memory Performance through Dynamic Transaction Reordering.
Proceedings of the High Performance Embedded Architectures and Compilers, 2009

2008
Experiences using adaptive concurrency in transactional memory with Lee's routing algorithm.
Proceedings of the 13th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, 2008

Investigating software Transactional Memory on clusters.
Proceedings of the 22nd IEEE International Symposium on Parallel and Distributed Processing, 2008

DiSTM: A Software Transactional Memory Framework for Clusters.
Proceedings of the 2008 International Conference on Parallel Processing, 2008

Lee-TM: A Non-trivial Benchmark Suite for Transactional Memory.
Proceedings of the Algorithms and Architectures for Parallel Processing, 2008

Advanced Concurrency Control for Transactional Memory Using Transaction Commit Rate.
Proceedings of the Euro-Par 2008, 2008


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