Arvindh Iyer

According to our database, Arvindh Iyer authored at least 2 papers between 2016 and 2022.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2022

An 182mW 1-60Gb/s Configurable PAM-4/NRZ Transceiver for Large Scale ASIC Integration in 7nm FinFET Technology.

Namik Kocaman, Ullas Singh, Bharath Raghavan, Arvindh Iyer, Kumar Thasari, Saurabh Surana, Jun Won Jung, Jaehun Jeong, Heng Zhang, Anand Vasani, Yonghyun Shim, Zhi Huang, Adesh Garg, Hsiang-bin Lee, Bo Wu, Feifei Liu, Ray Wang, Matthew Loh, Alex Wang, Mario Caresosa, Bo Zhang, Afshin Momtaz

Proceedings of the IEEE International Solid-State Circuits Conference, 2022

2016

A 3.8 mW/Gbps Quad-Channel 8.5-13 Gbps Serial Link With a 5 Tap DFE and a 4 Tap Transmit FFE in 28 nm CMOS.

Namik Kocaman, Tamer A. Ali, Lakshmi P. Rao, Ullas Singh, Mohammed M. Abdul-Latif, Yang Liu, Amr Amin Hafez, Henry Park, Anand Vasani, Zhi Huang, Arvindh Iyer, Bo Zhang, Afshin Momtaz

IEEE J. Solid State Circuits, 2016