Arvindh Iyer
According to our database1,
Arvindh Iyer authored at least 5 papers
between 2015 and 2026.
Collaborative distances:
Collaborative distances:
Timeline
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2026
8.6 A 280mW 112Gb/s PAM-4/NRZ Transceiver for Low-Power IOs in 5nm FinFET Technology.
Proceedings of the IEEE International Solid-State Circuits Conference, 2026
2025
An 800GbE PAM-4 PHY Transceiver for 42 dB Copper and Direct-Drive Optical Applications in 7 nm.
IEEE Solid State Circuits Lett., 2025
An 800GbE PAM-4 PHY Transceiver that Supports 42dB Copper and Direct-Drive Optical Applications in 7nm.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2025
2022
An 182mW 1-60Gb/s Configurable PAM-4/NRZ Transceiver for Large Scale ASIC Integration in 7nm FinFET Technology.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022
2015
A 3.8 mW/Gbps quad-channel 8.5-13 Gbps serial link with a 5-tap DFE and a 4-tap transmit FFE in 28 nm CMOS.
Proceedings of the Symposium on VLSI Circuits, 2015