Ashwin Raghunathan

According to our database, Ashwin Raghunathan authored at least 7 papers between 2004 and 2022.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2022

A Sub-100 Fs RMS_jitter 20 GHz Fractional-N Analog PLL With a BAW Resonator Based On-Chip 2.5 GHz Reference.

Sachin Kalia, Salvatore Finocchiaro, Tolga Dinc, Bichoy Bahr, Ashwin Raghunathan, Gerd Schuppener, Siraj Akhtar, Tobias Fritz, Baher Haroun, Benjamin Cook, Swaminathan Sankaran

IEEE J. Solid State Circuits, 2022

2020

A Simple Linear Time-Variant Theory of Superregeneration.

Ashwin Raghunathan, Thomas H. Lee

Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

2018

A 125 pJ/hit 5 mW 28 GHz Superregenerative Receiver with Automatic Gain Control and Energy Efficient Startup for Burst Mode IoE Applications.

Ashwin Raghunathan, Thomas H. Lee

Proceedings of the 44th IEEE European Solid State Circuits Conference, 2018

2010

On-Chip Delay Measurement Based Response Analysis for Timing Characterization.

Ramyanshu Datta, Antony Sebastine, Ashwin Raghunathan, Gary D. Carpenter, Kevin J. Nowka, Jacob A. Abraham

J. Electron. Test., 2010

2004

Prediction of Analog Performance Parameters Using Oscillation Based Test.

Ashwin Raghunathan, Hongjoong Shin, Jacob A. Abraham, Abhijit Chatterjee

Proceedings of the 22nd IEEE VLSI Test Symposium (VTS 2004), 2004

Quasi-Oscillation Based Test for Improved Prediction of Analog Performance Parameters.

Ashwin Raghunathan, Ji Hwan (Paul) Chun, Jacob A. Abraham, Abhijit Chatterjee

Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

On-chip delay measurement for silicon debug.

Ramyanshu Datta, Antony Sebastine, Ashwin Raghunathan, Jacob A. Abraham

Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, 2004