Ramyanshu Datta

According to our database, Ramyanshu Datta authored at least 13 papers between 2004 and 2010.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2010

On-Chip Delay Measurement Based Response Analysis for Timing Characterization.

Ramyanshu Datta, Antony Sebastine, Ashwin Raghunathan, Gary D. Carpenter, Kevin J. Nowka, Jacob A. Abraham

J. Electron. Test., 2010

Case studies of mixed-signal DFT.

Ramyanshu Datta, Mahit Warhadpande, Dale Heaton, S. Aarthi, Ram Jonnavithula

Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010

2009

A novel architecture for on-chip path delay measurement.

Xiaoxiao Wang, Mohammad Tehranipoor, Ramyanshu Datta

Proceedings of the 2009 IEEE International Test Conference, 2009

2008

Controllability of Static CMOS Circuits for Timing Characterization.

Ramyanshu Datta, Ravi Gupta, Antony Sebastine, Jacob A. Abraham, Manuel A. d'Abreu

J. Electron. Test., 2008

Performance-Optimized Design for Parametric Reliability.

Ramyanshu Datta, Jacob A. Abraham, Abdulkadir Utku Diril, Abhijit Chatterjee, Kevin J. Nowka

J. Electron. Test., 2008

Path-RO: a novel on-chip critical path delay measurement under process variations.

Xiaoxiao Wang, Mohammad Tehranipoor, Ramyanshu Datta

Proceedings of the 2008 International Conference on Computer-Aided Design, 2008

2006

A Scheme for On-Chip Timing Characterization.

Ramyanshu Datta, Gary D. Carpenter, Kevin J. Nowka, Jacob A. Abraham

Proceedings of the 24th IEEE VLSI Test Symposium (VTS 2006), 30 April, 2006

Adaptive Design for Performance-Optimized Robustness.

Ramyanshu Datta, Jacob A. Abraham, Abdulkadir Utku Diril, Abhijit Chatterjee, Kevin J. Nowka

Proceedings of the 21th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2006), 2006

2005

Testing and debugging delay faults in dynamic circuits.

Ramyanshu Datta, Sani R. Nassif, Robert K. Montoye, Jacob A. Abraham

Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005

2004

Tri-Scan: A Novel DFT Technique for CMOS Path Delay Fault Testing.

Ramyanshu Datta, Ravi Gupta, Antony Sebastine, Jacob A. Abraham, Manuel A. d'Abreu

Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

A low latency and low power dynamic Carry Save Adder.

Ramyanshu Datta, Jacob A. Abraham, Robert K. Montoye, Wendy Belluomini, Hung C. Ngo, Chandler McDowell, Jente B. Kuang, Kevin J. Nowka

Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

On-chip delay measurement for silicon debug.

Ramyanshu Datta, Antony Sebastine, Ashwin Raghunathan, Jacob A. Abraham

Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, 2004

Delay fault testing and silicon debug using scan chains.

Ramyanshu Datta, Antony Sebastine, Jacob A. Abraham

Proceedings of the 9th European Test Symposium, 2004