Ashwini K. Nanda

According to our database1, Ashwini K. Nanda authored at least 30 papers between 1991 and 2007.

Collaborative distances:


IEEE Fellow

IEEE Fellow 2010, "For leadership in high performance computer systems".



In proceedings 
PhD thesis 




Cell/B.E. blades: Building blocks for scalable, real-time, interactive, and digital media servers.
IBM Journal of Research and Development, 2007

Speech recognition systems on the Cell Broadband Engine processor.
IBM Journal of Research and Development, 2007

IBM Journal of Research and Development, 2007

High-performance server systems and the next generation of online games.
IBM Systems Journal, 2006

Guest Editors' Introduction: Evaluating Servers with Commercial Workloads.
IEEE Computer, 2003

Shared cache architectures for decision support systems.
Perform. Eval., 2002

High-throughout coherence control and hardware messaging in Everest.
IBM Journal of Research and Development, 2001

Using Switch Directories to Speed Up Cache-to-Cache Transfers in CC-NUMA Multiprocessors.
Proceedings of the 14th International Parallel & Distributed Processing Symposium (IPDPS'00), 2000

High-Throughput Coherence Controllers.
Proceedings of the Sixth International Symposium on High-Performance Computer Architecture, 2000

MemorIES: A Programmable, Real-Time Hardware Emulation Tool for Multiprocessor Server Design.
Proceedings of the ASPLOS-IX Proceedings of the 9th International Conference on Architectural Support for Programming Languages and Operating Systems, 2000

Coherence Controller Architectures for Scalable Shared-Memory Multiprocessors.
IEEE Trans. Computers, 1999

Measurement, analysis and performance improvement of the Apache Web server.
Proceedings of the IEEE International Performance Computing and Communications Conference, 1999

Design and Performance of Directory Caches for Scalable Shared Memory Multiprocessors.
Proceedings of the Fifth International Symposium on High-Performance Computer Architecture, 1999

Second Workshop on Computer Architecture Evaluation Using Commercial Workloads.
Proceedings of the Fifth International Symposium on High-Performance Computer Architecture, 1999

Energy optimization of multilevel cache architectures for RISC and CISC processors.
IEEE Trans. VLSI Syst., 1998

The Misprediction Recovery Cache.
International Journal of Parallel Programming, 1998

The Design of COMPASS: An Execution Driven Simulator for Commercial Applications Running on Shared Memory Multiprocessors.

Performance of Multistage Bus Networks for a Distributed Shared Memory Multiprocessor.
IEEE Trans. Parallel Distrib. Syst., 1997

Coherence Controller Architectures for SMP-Based CC-NUMA Multiprocessors.
Proceedings of the 24th International Symposium on Computer Architecture, 1997

Accuracy and Speedup of Parallel Trace-Driven Architectural Simulation.
Proceedings of the 11th International Parallel Processing Symposium (IPPS '97), 1997

Integrating a Misprediction Recovery Cache (MRC) into a Superscalar Pipeline.
Proceedings of the 29th Annual IEEE/ACM International Symposium on Microarchitecture, 1996

Energy optimization of multi-level processor cache architectures.
Proceedings of the 1995 International Symposium on Low Power Design 1995, 1995

Performance and Reliability of the Multistage Bus Network.
Proceedings of the 1994 International Conference on Parallel Processing, 1994

Design and Analysis of Cache Coherent Multistage Interconnection Networks.
IEEE Trans. Computers, 1993

Efficient Mapping of Applications on Cache Based Multiprocessors.
J. Parallel Distrib. Comput., 1993

Mapping Applications onto a Cache Coherent Multiprocessor.
Proceedings of the Proceedings Supercomputing '92, 1992

A Formal Specification and Verification Technique for Cache Coherence Protocols.
Proceedings of the 1992 International Conference on Parallel Processing, 1992

Scheduling Directed Task Graphs on Multiprocessors Using Simulated Annealing.
Proceedings of the 12th International Conference on Distributed Computing Systems, 1992

Analysis of Directory Based Cache Coherence Schemes with Multistage Networks.
Proceedings of the ACM 20th Annual Conference on Computer Science, 1992

Multistage bus network (MBN): an interconnection network for cache coherent multiprocessors.
Proceedings of the Third IEEE Symposium on Parallel and Distributed Processing, 1991