Ashwini K. Nanda

According to our database, Ashwini K. Nanda authored at least 30 papers between 1991 and 2007.

Collaborative distances:

• Dijkstra number of three.
• Erdős number of four.

2007

Cell/B.E. blades: Building blocks for scalable, real-time, interactive, and digital media servers.

Ashwini K. Nanda, J. Randal Moulic, Robert E. Hanson, Gottfried Goldrian, Michael N. Day, Bruce D. D'Amora, Sreeni Kesavarapu

IBM J. Res. Dev., 2007

Speech recognition systems on the Cell Broadband Engine processor.

Yang Liu, Holger Jones, Sheila Vaidya, Michael Perrone, Borivoj Tydlitát, Ashwini K. Nanda

IBM J. Res. Dev., 2007

Preface.

H. Peter Hofstee, Ashwini K. Nanda, John J. Ritsko

IBM J. Res. Dev., 2007

2006

High-performance server systems and the next generation of online games.

Bruce D'Amora, Ashwini K. Nanda, Karen A. Magerlein, Atman Binstock, Bernard Yee

IBM Syst. J., 2006

2003

Guest Editors' Introduction: Evaluating Servers with Commercial Workloads.

Kimberly Keeton, Russell M. Clapp, Ashwini K. Nanda

Computer, 2003

2002

Shared cache architectures for decision support systems.

Michel Dubois, Jaeheon Jeong, Ashwini K. Nanda

Perform. Evaluation, 2002

2001

Measurement, Analysis and Performance Improvement of the Apache Web Server.

Yiming Hu, Ashwini K. Nanda, Qing Yang

Int. J. Comput. Their Appl., 2001

High-throughout coherence control and hardware messaging in Everest.

Ashwini K. Nanda, Anthony-Trung Nguyen, Maged M. Michael, Douglas J. Joseph

IBM J. Res. Dev., 2001

2000

Using Switch Directories to Speed Up Cache-to-Cache Transfers in CC-NUMA Multiprocessors.

Ravi R. Iyer, Laxmi N. Bhuyan, Ashwini K. Nanda

Proceedings of the 14th International Parallel & Distributed Processing Symposium (IPDPS'00), 2000

High-Throughput Coherence Controllers.

Ashwini K. Nanda, Anthony-Trung Nguyen, Maged M. Michael, Douglas J. Joseph

Proceedings of the Sixth International Symposium on High-Performance Computer Architecture, 2000

MemorIES: A Programmable, Real-Time Hardware Emulation Tool for Multiprocessor Server Design.

Ashwini K. Nanda, Kwok-Ken Mak, Krishnan Sugavanam, Ramendra K. Sahoo, Vijayaraghavan Soundararajan, T. Basil Smith

Proceedings of the ASPLOS-IX Proceedings of the 9th International Conference on Architectural Support for Programming Languages and Operating Systems, 2000

1999

Coherence Controller Architectures for Scalable Shared-Memory Multiprocessors.

Maged M. Michael, Ashwini K. Nanda, Beng-Hong Lim

IEEE Trans. Computers, 1999

Design and Performance of Directory Caches for Scalable Shared Memory Multiprocessors.

Maged M. Michael, Ashwini K. Nanda

Proceedings of the Fifth International Symposium on High-Performance Computer Architecture, 1999

Second Workshop on Computer Architecture Evaluation Using Commercial Workloads.

Russell M. Clapp, Ashwini K. Nanda, Josep Torrellas

Proceedings of the Fifth International Symposium on High-Performance Computer Architecture, 1999

1998

Energy optimization of multilevel cache architectures for RISC and CISC processors.

Uming Ko, Poras T. Balsara, Ashwini K. Nanda

IEEE Trans. Very Large Scale Integr. Syst., 1998

The Misprediction Recovery Cache.

Ashwini K. Nanda, James O. Bondi, Simonjit Dutta

Int. J. Parallel Program., 1998

The Design of COMPASS: An Execution Driven Simulator for Commercial Applications Running on Shared Memory Multiprocessors.

Ashwini K. Nanda, Yiming Hu, Moriyoshi Ohara, Caroline Benveniste, Mark Giampapa, Maged M. Michael

Proceedings of the 12th International Parallel Processing Symposium / 9th Symposium on Parallel and Distributed Processing (IPPS/SPDP '98), March 30, 1998

1997

Performance of Multistage Bus Networks for a Distributed Shared Memory Multiprocessor.

Laxmi N. Bhuyan, Ravi R. Iyer, Tahsin Askar, Ashwini K. Nanda, Mohan Kumar

IEEE Trans. Parallel Distributed Syst., 1997

Coherence Controller Architectures for SMP-Based CC-NUMA Multiprocessors.

Maged M. Michael, Ashwini K. Nanda, Beng-Hong Lim, Michael L. Scott

Proceedings of the 24th International Symposium on Computer Architecture, 1997

Accuracy and Speedup of Parallel Trace-Driven Architectural Simulation.

Anthony-Trung Nguyen, Pradip Bose, Kattamuri Ekanadham, Ashwini K. Nanda, Maged M. Michael

Proceedings of the 11th International Parallel Processing Symposium (IPPS '97), 1997

1996

Integrating a Misprediction Recovery Cache (MRC) into a Superscalar Pipeline.

James O. Bondi, Ashwini K. Nanda, Simonjit Dutta

Proceedings of the 29th Annual IEEE/ACM International Symposium on Microarchitecture, 1996

1995

Energy optimization of multi-level processor cache architectures.

Uming Ko, Poras T. Balsara, Ashwini K. Nanda

Proceedings of the 1995 International Symposium on Low Power Design 1995, 1995

1994

Performance and Reliability of the Multistage Bus Network.

Laxmi N. Bhuyan, Ashwini K. Nanda, Tahsin Askar

Proceedings of the 1994 International Conference on Parallel Processing, 1994

1993

Design and Analysis of Cache Coherent Multistage Interconnection Networks.

Ashwini K. Nanda, Laxmi N. Bhuyan

IEEE Trans. Computers, 1993

Efficient Mapping of Applications on Cache Based Multiprocessors.

Ashwini K. Nanda, Laxmi N. Bhuyan

J. Parallel Distributed Comput., 1993

1992

Mapping Applications onto a Cache Coherent Multiprocessor.

Ashwini K. Nanda, Laxmi N. Bhuyan

Proceedings of the Proceedings Supercomputing '92, 1992

A Formal Specification and Verification Technique for Cache Coherence Protocols.

Ashwini K. Nanda, Laxmi N. Bhuyan

Proceedings of the 1992 International Conference on Parallel Processing, 1992

Scheduling Directed Task Graphs on Multiprocessors Using Simulated Annealing.

Ashwini K. Nanda, Doug DeGroot, Daniel L. Stenger

Proceedings of the 12th International Conference on Distributed Computing Systems, 1992

Analysis of Directory Based Cache Coherence Schemes with Multistage Networks.

Ashwini K. Nanda, Hong Jiang

Proceedings of the ACM 20th Annual Conference on Computer Science, 1992

1991

Multistage bus network (MBN): an interconnection network for cache coherent multiprocessors.

Laxmi N. Bhuyan, Ashwini K. Nanda

Proceedings of the Third IEEE Symposium on Parallel and Distributed Processing, 1991