Athanasios Milidonis

Orcid: 0000-0001-9408-2104

According to our database1, Athanasios Milidonis authored at least 31 papers between 2003 and 2022.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2022
Hardware Selection Approach For Custom UAVs.
Proceedings of the 26th Pan-Hellenic Conference on Informatics, 2022

2021
Secure Video Transmission System for UAV Applications.
Proceedings of the PCI 2021: 25th Pan-Hellenic Conference on Informatics, Volos, Greece, November 26, 2021

A high performance architecture for object detection in drones.
Proceedings of the PCI 2021: 25th Pan-Hellenic Conference on Informatics, Volos, Greece, November 26, 2021

A survey for UAV open-source telemetry protocols.
Proceedings of the PCI 2021: 25th Pan-Hellenic Conference on Informatics, Volos, Greece, November 26, 2021

2020
Architecture for Secure UAV Systems.
Proceedings of the PCI 2020: 24th Pan-Hellenic Conference on Informatics, 2020

Autonomous drone charging stations: A survey.
Proceedings of the PCI 2020: 24th Pan-Hellenic Conference on Informatics, 2020

2014
Stealth Assessment of Hardware Trojans in simple Processors.
Proceedings of the 18th Panhellenic Conference on Informatics, 2014

2013
An effective two-pattern test generator for Arithmetic BIST.
Comput. Electr. Eng., 2013

2012
Arithmetic module-based built-in self test architecture for two-pattern testing.
IET Comput. Digit. Tech., 2012

2011
A survey on throughput-efficient architectures for IEEE P1619 for shared storage media.
Proceedings of the 16th IEEE Symposium on Computers and Communications, 2011

High-throughput ASIC implementation of an encryption core for securing shared storage media.
Proceedings of the 17th International Conference on Digital Signal Processing, 2011

2010
Decoupled Processors Architecture for Accelerating Data Intensive Applications using Scratch-Pad Memory Hierarchy.
J. Signal Process. Syst., 2010

2009
A Top-Down Design Methodology for Ultrahigh-Performance Hashing Cores.
IEEE Trans. Dependable Secur. Comput., 2009

Low-power architecture with scratch-pad memory for accelerating embedded applications with run-time reuse.
IET Comput. Digit. Tech., 2009

2007
Automated framework for partitioning DSP applications in hybrid reconfigurable platforms.
Microprocess. Microsystems, 2007

A Low Power Design for Sbox Cryptographic Primitive of Advanced Encryption Standard for Mobile End-Users.
J. Low Power Electron., 2007

Interactive presentation: A decoupled architecture of processors with scratch-pad memory hierarchy.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

2006
High-Speed FPGA Implementation of Secure Hash Algorithm for IPSec and VPN Applications.
J. Supercomput., 2006

A design flow for speeding-up dsp applications in heterogeneous reconfigurable systems.
Microelectron. J., 2006

Temporal and System Level Modifications for High Speed VLSI Implementations of Cryptographic Core.
Proceedings of the 13th IEEE International Conference on Electronics, 2006

2005
A high-throughput, memory efficient architecture for computing the tile-based 2D discrete wavelet transform for the JPEG2000.
Integr., 2005

A method for partitioning applications in hybrid reconfigurable architectures.
Des. Autom. Embed. Syst., 2005

A methodology for partitioning DSP applications in hybrid reconfigurable systems.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

A high-throughput and memory efficient 2D discrete wavelet transform hardware architecture for JPEG2000 standard.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

A Framework for Partitioning Computational Intensive Applications in Hybrid Reconfigurable Platforms.
Proceedings of the 19th International Parallel and Distributed Processing Symposium (IPDPS 2005), 2005

Novel high throughput implementation of SHA-256 hash function through pre-computation technique.
Proceedings of the 12th IEEE International Conference on Electronics, 2005

2004
A Framework for Data Partitioning for C++ Data-Intensive Applications.
Des. Autom. Embed. Syst., 2004

An Automated C++ Code and Data Partitioning Framework for Data Management of Data-Intensive Applications.
Proceedings of the Software and Compilers for Embedded Systems, 8th International Workshop, 2004

Efficient implementation of the keyed-hash message authentication code (HMAC) using the SHA-1 hash function.
Proceedings of the 2004 11th IEEE International Conference on Electronics, 2004

A Partitioning Methodology for Accelerating Applications in Hybrid Reconfigurable Platforms.
Proceedings of the 2004 Design, 2004

2003
Power aware data type refinement on the HIPERLAN/2.
Proceedings of the 2003 10th IEEE International Conference on Electronics, 2003


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