Vasilis N. Thanasoulis

According to our database, Vasilis N. Thanasoulis authored at least 11 papers between 2006 and 2026.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2026

Characterization of Off-wafer Pulse Communication in BrainScaleS Neuromorphic System.

Bernhard Vogginger, Vasilis N. Thanasoulis, Johannes Partzsch, Christian Mayr

CoRR, March, 2026

2021

Delay-Based Neural Computation: Pulse Routing Architecture and Benchmark Application in FPGA.

Vasilis N. Thanasoulis, Bernhard Vogginger, Johannes Partzsch, Christian Mayr

Proceedings of the 28th IEEE International Conference on Electronics, 2021

2017

Pattern representation and recognition with accelerated analog neuromorphic systems.

Mihai A. Petrovici, Sebastian Schmitt, Johann Klähn, David Stöckel, Anna Schroeder, Guillaume Bellec, Johannes Bill, Oliver Breitwieser, Ilja Bytschok, Andreas Grübl, Maurice Güttler, Andreas Hartel, Stephan Hartmann, Dan Husmann de Oliveira, Kai Husmann, Sebastian Jeltsch, Vitali Karasenko, Mitja Kleider, Christoph Koke, Alexander Kononov, Christian Mauch, Paul Müller, Johannes Partzsch, Thomas Pfeil, Stefan Schiefer, Stefan Scholze, Anand Subramoney, Vasilis N. Thanasoulis, Bernhard Vogginger, Robert Legenstein, Wolfgang Maass, René Schüffny, Christian Mayr, Johannes Schemmel, Karlheinz Meier

CoRR, 2017

Pattern representation and recognition with accelerated analog neuromorphic systems.

Mihai A. Petrovici, Sebastian Schmitt, Johann Klähn, Robert D. St. Louis, Anna Schroeder, Guillaume Bellec, Johannes Bill, Oliver Breitwieser, Ilja Bytschok, Andreas Grübl, Maurice Güttler, Andreas Hartel, Stephan Hartmann, Dan Husmann de Oliveira, Kai Husmann, Sebastian Jeltsch, Vitali Karasenko, Mitja Kleider, Christoph Koke, Alexander Kononov, Christian Mauch, Eric Müller, Paul Müller, Johannes Partzsch, Thomas Pfeil, Stefan Schiefer, Stefan Scholze, Anand Subramoney, Vasilis N. Thanasoulis, Bernhard Vogginger, Robert Legenstein, Wolfgang Maass, René Schüffny, Christian Mayr, Johannes Schemmel, Karlheinz Meier

Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Neuromorphic hardware in the loop: Training a deep spiking network on the BrainScaleS wafer-scale system.

Sebastian Schmitt, Johann Klähn, Guillaume Bellec, Andreas Grübl, Maurice Güttler, Andreas Hartel, Stephan Hartmann, Dan Husmann de Oliveira, Kai Husmann, Sebastian Jeltsch, Vitali Karasenko, Mitja Kleider, Christoph Koke, Alexander Kononov, Christian Mauch, Eric Müller, Paul Müller, Johannes Partzsch, Mihai A. Petrovici, Stefan Schiefer, Stefan Scholze, Vasilis N. Thanasoulis, Bernhard Vogginger, Robert Legenstein, Wolfgang Maass, Christian Mayr, René Schüffny, Johannes Schemmel, Karlheinz Meier

Proceedings of the 2017 International Joint Conference on Neural Networks, 2017

2014

A pulse communication flow ready for accelerated neuromorphic experiments.

Vasilis N. Thanasoulis, Bernhard Vogginger, Johannes Partzsch, René Schüffny

Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

Configurable pulse routing architecture for accelerated multi-node neuromorphic systems.

Vasilis N. Thanasoulis, Johannes Partzsch, Bernhard Vogginger, René Schüffny

Proceedings of the 21st IEEE International Conference on Electronics, Circuits and Systems, 2014

2012

Long-term pulse stimulation and recording in an accelerated neuromorphic system.

Vasilis N. Thanasoulis, Johannes Partzsch, Bernhard Vogginger, Christian Mayr, René Schüffny

Proceedings of the 19th IEEE International Conference on Electronics, Circuits and Systems, 2012

Dedicated FPGA communication architecture and design for a large-scale neuromorphic system.

Vasilis N. Thanasoulis, Johannes Partzsch, Stephan Hartmann, Christian Mayr, René Schüffny

Proceedings of the 19th IEEE International Conference on Electronics, Circuits and Systems, 2012

2007

Server side hashing core exceeding 3 Gbps of throughput.

Harris E. Michail, George A. Panagiotakopoulos, Vasilis N. Thanasoulis, Athanasios Kakarountas, Costas E. Goutis

Int. J. Secur. Networks, 2007

2006

Temporal and System Level Modifications for High Speed VLSI Implementations of Cryptographic Core.

Harris E. Michail, Athanasios P. Kakarountas, Athanasios Milidonis, George A. Panagiotakopoulos, Vasilis N. Thanasoulis, Costas E. Goutis

Proceedings of the 13th IEEE International Conference on Electronics, 2006