Grigoris Dimitroulakos

Orcid: 0000-0001-7580-3914

According to our database1, Grigoris Dimitroulakos authored at least 54 papers between 2002 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

Online presence:

On csauthors.net:

Bibliography

2023
Simulating Software Evolution to Evaluate the Reliability of Early Decision-making among Design Alternatives toward Maintainability.
ACM Trans. Softw. Eng. Methodol., May, 2023

2020
Experimental (raw) Data of Statistical Comparison Between Formal and Simulated Models' Outcomes for CIBI vs. CVP General Problem.
Dataset, May, 2020

A Locality Optimizer for Loop-dominated Applications Based on Reuse Distance Analysis.
ACM Trans. Design Autom. Electr. Syst., 2020

A Retargetable MATLAB-to-C Compiler Exploiting Custom Instructions and Data Parallelism.
ACM Trans. Embed. Comput. Syst., 2020

2017
Early Evaluation of Implementation Alternatives of Composite Data Structures Toward Maintainability.
ACM Trans. Softw. Eng. Methodol., 2017

A MATLAB Vectorizing Compiler Targeting Application-Specific Instruction Set Processors.
ACM Trans. Design Autom. Electr. Syst., 2017

2016
Compiler-Directed Data Locality Optimization in MATLAB.
Proceedings of the 19th International Workshop on Software and Compilers for Embedded Systems, 2016

Matlab to C compilation targeting Application Specific Instruction Set Processors.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Automatic Generation of Code Analysis Tools: The CastQL Approach.
Proceedings of the 1st International Workshop on Real World Domain Specific Languages, 2016

2015
Reuse distance analysis for locality optimization in loop-dominated applications.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

2014
An early memory hierarchy evaluation simulator for multimedia applications.
Microprocess. Microsystems, 2014

2013
Compiling Scilab to high performance embedded multicore systems.
Microprocess. Microsystems, 2013

Dynamic source code analysis for memory hierarchy optimization in multimedia applications.
Proceedings of the 2013 Conference on Design and Architectures for Signal and Image Processing, 2013

2012

A flexible approach for compiling scilab to reconfigurable multi-core embedded systems.
Proceedings of the 7th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), 2012

MEMSCOPT: A source-to-source compiler for dynamic code analysis and loop transformations.
Proceedings of the 2012 Conference on Design and Architectures for Signal and Image Processing, 2012

XMSIM: A tool for early memory hierarchy evaluation.
Proceedings of the 2012 Conference on Design and Architectures for Signal and Image Processing, 2012

2010
XMSIM: Extensible Memory Simulator for Early Memory Hierarchy Evaluation.
Proceedings of the VLSI 2010 Annual Symposium - Selected papers, 2010

2009
Compiler assisted architectural exploration framework for coarse grained reconfigurable arrays.
J. Supercomput., 2009

Resource aware mapping on coarse grained reconfigurable arrays.
Microprocess. Microsystems, 2009

2008
Performance and Energy Consumption Improvements in Microprocessor Systems Utilizing a Coprocessor Data-Path.
J. Signal Process. Syst., 2008

Integrating high speed multipliers in Coarse Grain Reconfigurable Arrays.
Proceedings of the 2008 IEEE International Symposium on System-on-Chip, 2008

2007
Speedups and Energy Reductions From Mapping DSP Applications on an Embedded Reconfigurable System.
IEEE Trans. Very Large Scale Integr. Syst., 2007

Speedups in embedded systems with a high-performance coprocessor datapath.
ACM Trans. Design Autom. Electr. Syst., 2007

Exploring the speedups of embedded microprocessor systems utilizing a high-performance coprocessor data-path.
J. Supercomput., 2007

Design space exploration of an optimized compiler approach for a generic reconfigurable array architecture.
J. Supercomput., 2007

Performance Optimization of Embedded Applications in a Hybrid Reconfigurable Platform.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2007

Speedups and Energy Savings of Microprocessor Platforms with a Coarse-Grained Reconfigurable Data-Path.
Proceedings of the 21th International Parallel and Distributed Processing Symposium (IPDPS 2007), 2007

Improving performance and energy consumption in embedded microprocessor platforms with a flexible custom coprocessor data-path.
Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007

Compiler assisted architectural exploration for coarse grained reconfigurable arrays.
Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007

A unified evaluation framework for coarse grained reconfigurable array architectures.
Proceedings of the 4th Conference on Computing Frontiers, 2007

2006
Partitioning Methodology for Heterogeneous Reconfigurable Functional Units.
J. Supercomput., 2006

Performance Improvements from Partitioning Applications to FPGA Hardware in Embedded SoCs.
J. Supercomput., 2006

Performance Improvements in Microprocessor Systems Utilizing a Copressor Data-Path.
Proceedings of 2006 International Conference on Embedded Computer Systems: Architectures, 2006

Mapping DSP applications on processor/coarse-grain reconfigurable array architectures.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Resource constrained modulo scheduling for coarse-grained reconfigurable arrays.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Mapping DSP applications on processor systems with coarse-grain reconfigurable hardware.
Proceedings of the 20th International Parallel and Distributed Processing Symposium (IPDPS 2006), 2006

Design flow for optimizing performance in processor systems with on-chip coarse-grain reconfigurable logic.
Proceedings of the 20th International Parallel and Distributed Processing Symposium (IPDPS 2006), 2006

Exploring the design space of an optimized compiler approach for mesh-like coarse-grained reconfigurable architectures.
Proceedings of the 20th International Parallel and Distributed Processing Symposium (IPDPS 2006), 2006

2005
A high-throughput, memory efficient architecture for computing the tile-based 2D discrete wavelet transform for the JPEG2000.
Integr., 2005

Performance Gains from Partitioning Embedded Applications in Processor-FPGA SoCs.
Proceedings of the Integrated Circuit and System Design, 2005

An automated methodology for memory-conscious mapping of DSP applications on coarse-grain reconfigurable arrays.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

A high-throughput and memory efficient 2D discrete wavelet transform hardware architecture for JPEG2000 standard.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

A Compiler Method for Memory-Conscious Mapping of Applications on Coarse-Grained Reconfigurable Architectures.
Proceedings of the 19th International Parallel and Distributed Processing Symposium (IPDPS 2005), 2005

Partitioning DSP applications to different granularity reconfigurable hardware.
Proceedings of the 12th IEEE International Conference on Electronics, 2005

Performance Improvements using Coarse-Grain Reconfigurable Logic in Embedded SoCs.
Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), 2005

Accelerating Applications by Mapping Critical Kernels on Coarse-Grain Reconfigurable Hardware in Hybrid Systems.
Proceedings of the 13th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2005), 2005

Speedups from Partitioning Critical Software Parts to Coarse-Grain Reconfigurable Hardware.
Proceedings of the 16th IEEE International Conference on Application-Specific Systems, 2005

Alleviating the Data Memory Bandwidth Bottleneck in Coarse-Grained Reconfigurable Arrays.
Proceedings of the 16th IEEE International Conference on Application-Specific Systems, 2005

2004
A Framework for Data Partitioning for C++ Data-Intensive Applications.
Des. Autom. Embed. Syst., 2004

An Automated C++ Code and Data Partitioning Framework for Data Management of Data-Intensive Applications.
Proceedings of the Software and Compilers for Embedded Systems, 8th International Workshop, 2004

2003
An ultra high speed architecture for VLSI implementation of hash functions.
Proceedings of the 2003 10th IEEE International Conference on Electronics, 2003

Power aware data type refinement on the HIPERLAN/2.
Proceedings of the 2003 10th IEEE International Conference on Electronics, 2003

2002
An efficient VLSI implementation for forward and inverse wavelet transform for JPEG2000.
Proceedings of the 14th International Conference on Digital Signal Processing, 2002


  Loading...