Ayaskant Shrivastava

According to our database1, Ayaskant Shrivastava authored at least 4 papers between 2015 and 2016.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2016
A 2.7 mW/Channel 48-1000 MHz Direct Sampling Full-Band Cable Receiver.
IEEE J. Solid State Circuits, 2016

2015
A 5 GS/s 150 mW 10 b SHA-Less Pipelined/SAR Hybrid ADC for Direct-Sampling Systems in 28 nm CMOS.
IEEE J. Solid State Circuits, 2015




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