Juo-Jung Hung

According to our database1, Juo-Jung Hung authored at least 11 papers between 2005 and 2016.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2016
A 2.7 mW/Channel 48-1000 MHz Direct Sampling Full-Band Cable Receiver.
IEEE J. Solid State Circuits, 2016

27.6 A 4GS/s 13b pipelined ADC with capacitor and amplifier sharing in 16nm CMOS.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

2015
A 5 GS/s 150 mW 10 b SHA-Less Pipelined/SAR Hybrid ADC for Direct-Sampling Systems in 28 nm CMOS.
IEEE J. Solid State Circuits, 2015



2013
A 240-mW 2.1-GS/s 52-dB SNDR Pipeline ADC Using MDAC Equalization.
IEEE J. Solid State Circuits, 2013

2012
A 12-Bit 3 GS/s Pipeline ADC With 0.4 mm<sup>2</sup> and 500 mW in 40 nm Digital CMOS.
IEEE J. Solid State Circuits, 2012

A 240mW 2.1GS/s 12b pipeline ADC using MDAC equalization.
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012

2009
An Embedded 65 nm CMOS Baseband IQ 48 MHz-1 GHz Dual Tuner for DOCSIS 3.0.
IEEE J. Solid State Circuits, 2009


2005
A 77 GHz SiGe sub-harmonic balanced mixer.
IEEE J. Solid State Circuits, 2005


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