Hemasundar Mohan Geddada

According to our database1, Hemasundar Mohan Geddada authored at least 9 papers between 2011 and 2016.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Links

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Bibliography

2016
27.6 A 4GS/s 13b pipelined ADC with capacitor and amplifier sharing in 16nm CMOS.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

2015
Efficient Broadband Current-Mode Adder- Quantizer Design for Continuous-Time Sigma-Delta Modulators.
IEEE Trans. Very Large Scale Integr. Syst., 2015

Design Techniques to Improve Blocker Tolerance of Continuous-Time ΔΣ ADCs.
IEEE Trans. Very Large Scale Integr. Syst., 2015

A 5 GS/s 150 mW 10 b SHA-Less Pipelined/SAR Hybrid ADC for Direct-Sampling Systems in 28 nm CMOS.
IEEE J. Solid State Circuits, 2015


2014
Blocker tolerant wideband continuous time sigma-delta modulator for wireless applications.
Proceedings of the IEEE 57th International Midwest Symposium on Circuits and Systems, 2014

2013
A current-mode flash ADC for low-power continuous-time sigma delta modulators.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

2012
Blocker and jitter tolerant wideband ΣΔ modulators.
Proceedings of the 55th IEEE International Midwest Symposium on Circuits and Systems, 2012

2011
Fully balanced low-noise transconductance amplifiers with P1dB > 0dBm in 45nm CMOS.
Proceedings of the 37th European Solid-State Circuits Conference, 2011


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