Baolei Mao

Orcid: 0000-0002-4542-3037

According to our database1, Baolei Mao authored at least 15 papers between 2014 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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In proceedings 
Article 
PhD thesis 
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Links

Online presence:

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Bibliography

2024
Hardware/software security co-verification and vulnerability detection: An information flow perspective.
Integr., January, 2024

2022
Bisers: An Efficient DHCPv6 Bounding Solution.
Proceedings of the 22nd IEEE International Conference on Communication Technology, 2022

2021
Website Fingerprinting Attack Through Persistent Attack of Student.
Proceedings of the 7th IEEE International Conference on Cloud Computing and Intelligent Systems, 2021

Leveraging Application Complexity Partition for Android Malware Detection.
Proceedings of the 7th IEEE International Conference on Cloud Computing and Intelligent Systems, 2021

2020
Android Malware Detection Using Fine-Grained Features.
Sci. Program., 2020

A formal model for proving hardware timing properties and identifying timing channels.
Integr., 2020

2019
Theorem proof based gate level information flow tracking for hardware security verification.
Comput. Secur., 2019

2018
Quantitative Analysis of Timing Channel Security in Cryptographic Hardware Design.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

Towards Quantified Data Analysis of Information Flow Tracking for Secure System Design.
IEEE Access, 2018

Leaks or Not: A Framework for Evaluating Cache Timing Side Channel Attacks in SGX.
Proceedings of the 2018 IEEE SmartWorld, 2018

2017
A Simplifying Logic Approach for Gate Level Information Flow Tracking.
Proceedings of the Communications and Networking, 2017

2016
Detecting Hardware Trojans with Gate-Level Information-Flow Tracking.
Computer, 2016

2015
Quantifying Timing-Based Information Flow in Cryptographic Hardware.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015

2014
Gate-Level Information Flow Tracking for Security Lattices.
ACM Trans. Design Autom. Electr. Syst., 2014

A bottom-up approach to verifiable embedded system information flow security.
IET Inf. Secur., 2014


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