Jason Oberg

Orcid: 0009-0002-8327-6696

According to our database¹, Jason Oberg authored at least 30 papers between 2009 and 2023.

Collaborative distances:

Dijkstra number² of four.
Erdős number³ of four.

Timeline

Legend:

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In proceedings

Article

PhD thesis

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Links

On csauthors.net:

Bibliography

2023

A Framework for Design, Verification, and Management of SoC Access Control Systems.

[BibT_eX]

[DOI]

IEEE Trans. Computers, February, 2023

Security Verification of the OpenTitan Hardware Root of Trust.

[BibT_eX]

[DOI]

IEEE Secur. Priv., 2023

2021

Special Session: CAD for Hardware Security - Automation is Key to Adoption of Solutions.

[BibT_eX]

[DOI]

Proceedings of the 39th IEEE VLSI Test Symposium, 2021

Seeds of SEED: Building and Verifying Foundationally Isolated Hardware Architectures.

[BibT_eX]

[DOI]

Jason Oberg

Proceedings of the 2021 International Symposium on Secure and Private Execution Environment Design (SEED), 2021

2018

Innovative practices on challenges, opportunities, and solutions to hardware security.

[BibT_eX]

[DOI]

Proceedings of the 36th IEEE VLSI Test Symposium, 2018

2016

Detecting Hardware Trojans with Gate-Level Information-Flow Tracking.

[BibT_eX]

[DOI]

Computer, 2016

2015

Quantifying Timing-Based Information Flow in Cryptographic Hardware.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015

2014

Testing Hardware Security Properties and Identifying Timing Channels /.

[BibT_eX]

[DOI]

Jason K. Oberg

PhD thesis, 2014

Gate-Level Information Flow Tracking for Security Lattices.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2014

Leveraging Gate-Level Properties to Identify Hardware Timing Channels.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

Networks on Chip with Provable Security Properties.

[BibT_eX]

[DOI]

IEEE Micro, 2014

Sapper: a language for hardware-level security policy enforcement.

[BibT_eX]

[DOI]

Vasanth Ram Rajarathinam

Proceedings of the Architectural Support for Programming Languages and Operating Systems, 2014

2013

A software-based dynamic-warp scheduling approach for load-balancing the Viola-Jones face detection algorithm on GPUs.

[BibT_eX]

[DOI]

J. Parallel Distributed Comput., 2013

Expanding Gate Level Information Flow Tracking for Multilevel Security.

[BibT_eX]

[DOI]

IEEE Embed. Syst. Lett., 2013

Eliminating Timing Information Flows in a Mix-Trusted System-on-Chip.

[BibT_eX]

[DOI]

Jason Oberg

Timothy Sherwood

Ryan Kastner

IEEE Des. Test, 2013

Position paper: Sapper - a language for provable hardware policy enforcement.

[BibT_eX]

[DOI]

Vasanth Ram Rajarathinam

Proceedings of the 2013 ACM SIGPLAN Workshop on Programming Languages and Analysis for Security, 2013

SurfNoC: a low latency and provably non-interfering approach to secure networks-on-chip.

[BibT_eX]

[DOI]

Proceedings of the 40th Annual International Symposium on Computer Architecture, 2013

A practical testing framework for isolating hardware timing channels.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2013

2012

On the Complexity of Generating Gate Level Information Flow Tracking Logic.

[BibT_eX]

[DOI]

IEEE Trans. Inf. Forensics Secur., 2012

Simultaneous information flow security and circuit redundancy in Boolean gates.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012

Random decision tree body part recognition using FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 22nd International Conference on Field Programmable Logic and Applications (FPL), 2012

2011

Simulate and Eliminate: A Top-to-Bottom Design Methodology for Automatic Generation of Application Specific Architectures.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

Theoretical Fundamentals of Gate Level Information Flow Tracking.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

Caisson: a hardware description language for secure information flow.

[BibT_eX]

[DOI]

Proceedings of the 32nd ACM SIGPLAN Conference on Programming Language Design and Implementation, 2011

Crafting a usable microkernel, processor, and I/O system with strict and provable information flow security.

[BibT_eX]

[DOI]

Proceedings of the 38th International Symposium on Computer Architecture (ISCA 2011), 2011

Information flow isolation in I2C and USB.

[BibT_eX]

[DOI]

Proceedings of the 48th Design Automation Conference, 2011

2010

Minimal Multi-threading: Finding and Removing Redundant Instructions in Multi-threaded Processors.

[BibT_eX]

[DOI]

Proceedings of the 43rd Annual IEEE/ACM International Symposium on Microarchitecture, 2010

Accelerating Viola-Jones Face Detection to FPGA-Level Using GPUs.

[BibT_eX]

[DOI]

Proceedings of the 18th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2010

Theoretical analysis of gate level information flow tracking.

[BibT_eX]

[DOI]

Proceedings of the 47th Design Automation Conference, 2010

2009

Fpga-based face detection system using Haar classifiers.

[BibT_eX]

[DOI]

Proceedings of the ACM/SIGDA 17th International Symposium on Field Programmable Gate Arrays, 2009

Jason Oberg

Timeline

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On csauthors.net:

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