Wei Hu

Orcid: 0000-0001-6738-4297

Affiliations:
  • University of California San Diego, Department of Computer Science and Engineering, La Jolla, CA, USA
  • Northwestern Polytechnical University, School of Automation, Xi'an, China (former)


According to our database1, Wei Hu authored at least 60 papers between 2007 and 2024.

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Bibliography

2024
Provably Secure Asymmetric PAKE Protocol for Protecting IoT Access.
IEEE Internet Things J., February, 2024

Hardware/software security co-verification and vulnerability detection: An information flow perspective.
Integr., January, 2024

X-Attack 2.0: The Risk of Power Wasters and Satisfiability Don't-Care Hardware Trojans to Shared Cloud FPGAs.
IEEE Access, 2024

2023
A Publicly Verifiable E-Voting System Based on Biometrics.
Cryptogr., September, 2023

Design for Assurance: Employing Functional Verification Tools for Thwarting Hardware Trojan Threat in 3PIPs.
CoRR, 2023

Hunting for Hardware Trojan in Gate Netlist: A Stacking Ensemble Learning Perspective.
Proceedings of the IEEE International Test Conference in Asia, 2023

Maximizing Network Reliability in Large Scale Infrastructure Networks: A Heat Conduction Model Perspective.
Proceedings of the 15th International Conference on Machine Learning and Computing, 2023

Automated Hardware Trojan Detection at LUT Using Explainable Graph Neural Networks.
Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023

Security Verification of RISC-V System Based on ISA Level Information Flow Tracking.
Proceedings of the 32nd IEEE Asian Test Symposium, 2023

Verifying RISC-V Privilege Transition Integrity Through Symbolic Execution.
Proceedings of the 32nd IEEE Asian Test Symposium, 2023

2022
Hardware Information Flow Tracking.
ACM Comput. Surv., 2022

Towards Automatic Property Generation for SoC Security Verification.
Proceedings of the 19th International SoC Design Conference, 2022

Accelerating SoC Security Verification and Vulnerability Detection Through Symbolic Execution.
Proceedings of the 19th International SoC Design Conference, 2022

Hardware Trojan Detection at LUT: Where Structural Features Meet Behavioral Characteristics.
Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2022

Integrating Information Flow Tracking into High-Level Synthesis Design Flow.
Behavioral Synthesis for Hardware Security, 2022

2021
An Overview of Hardware Security and Trust: Threats, Countermeasures, and Design Tools.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

Accelerating hardware security verification and vulnerability detection through state space reduction.
Comput. Secur., 2021

Identifying Specious LUTs for Satisfiability Don't Care Trojan Detection.
Proceedings of the 34th IEEE International System-on-Chip Conference, 2021

Developing Formal Models for Measuring Fault Effects Using Functional EDA Tools.
Proceedings of the IEEE International Test Conference in Asia, 2021

A Correlation Fault Attack on Rotating S-Box Masking AES.
Proceedings of the Asian Hardware Oriented Security and Trust Symposium, 2021

2020
Memory-Based High-Level Synthesis Optimizations Security Exploration on the Power Side-Channel.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Machine-Learning-Based Side-Channel Leakage Detection in Electronic System-Level Synthesis.
IEEE Netw., 2020

A formal model for proving hardware timing properties and identifying timing channels.
Integr., 2020

A Unified Model for Gate Level Propagation Analysis.
CoRR, 2020

A Standardized ICS Network Data Processing Flow With Generative Model in Anomaly Detection.
IEEE Access, 2020

X-Attack: Remote Activation of Satisfiability Don't-Care Hardware Trojans on Shared FPGAs.
Proceedings of the 30th International Conference on Field-Programmable Logic and Applications, 2020

A Unified Formal Model for Proving Security and Reliability Properties.
Proceedings of the 29th IEEE Asian Test Symposium, 2020

Feedback-based Channel Gain Complement and Cluster-based Quantization for Physical Layer Key Generation.
Proceedings of the Asian Hardware Oriented Security and Trust Symposium, 2020

2019
Theorem proof based gate level information flow tracking for hardware security verification.
Comput. Secur., 2019

Leveraging Unspecified Functionality in Obfuscated Hardware for Trojan and Fault Attacks.
Proceedings of the Asian Hardware Oriented Security and Trust Symposium, 2019

2018
Quantitative Analysis of Timing Channel Security in Cryptographic Hardware Design.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

Towards Quantified Data Analysis of Information Flow Tracking for Secure System Design.
IEEE Access, 2018

Property Based Formal Security Verification for Hardware Trojan Detection.
Proceedings of the 3rd IEEE International Verification and Security Workshop, 2018

Property specific information flow analysis for hardware security verification.
Proceedings of the International Conference on Computer-Aided Design, 2018

Examining the consequences of high-level synthesis optimizations on power side-channel.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

Security Path Verification Through Joint Information Flow Analysis.
Proceedings of the 2018 IEEE Asia Pacific Conference on Circuits and Systems, 2018

2017
Identifying and Measuring Security Critical Path for Uncovering Circuit Vulnerabilities.
Proceedings of the 18th International Workshop on Microprocessor and SOC Test and Verification, 2017

Why you should care about don't cares: Exploiting internal don't care conditions for hardware Trojans.
Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

Clepsydra: Modeling timing flows in hardware designs.
Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

Register transfer level information flow tracking for provably secure hardware design.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Arbitrary Precision and Complexity Tradeoffs for Gate-Level Information Flow Tracking.
Proceedings of the 54th Annual Design Automation Conference, 2017

A Simplifying Logic Approach for Gate Level Information Flow Tracking.
Proceedings of the Communications and Networking, 2017

2016
Detecting Hardware Trojans with Gate-Level Information-Flow Tracking.
Computer, 2016

Generating optimized gate level information flow tracking logic for enforcing multilevel security.
Autom. Control. Comput. Sci., 2016

Towards Property Driven Hardware Security.
Proceedings of the 17th International Workshop on Microprocessor and SOC Test and Verification, 2016

Imprecise security: quality and complexity tradeoffs for hardware information flow tracking.
Proceedings of the 35th International Conference on Computer-Aided Design, 2016

Quantifying hardware security using joint information flow analysis.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

2015
Quantifying Timing-Based Information Flow in Cryptographic Hardware.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015

2014
Gate-Level Information Flow Tracking for Security Lattices.
ACM Trans. Design Autom. Electr. Syst., 2014

A bottom-up approach to verifiable embedded system information flow security.
IET Inf. Secur., 2014

Energy-efficient border intrusion detection using wireless sensors network.
EURASIP J. Wirel. Commun. Netw., 2014

2013
Expanding Gate Level Information Flow Tracking for Multilevel Security.
IEEE Embed. Syst. Lett., 2013

Towards a Moderate-Granularity Incremental Clustering Algorithm for GPU.
Proceedings of the 2013 International Conference on Cyber-Enabled Distributed Computing and Knowledge Discovery, 2013

Improvements the Seccomp Sandbox Based on PBE Theory.
Proceedings of the 27th International Conference on Advanced Information Networking and Applications Workshops, 2013

2012
On the Complexity of Generating Gate Level Information Flow Tracking Logic.
IEEE Trans. Inf. Forensics Secur., 2012

Simultaneous information flow security and circuit redundancy in Boolean gates.
Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012

2011
Theoretical Fundamentals of Gate Level Information Flow Tracking.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

Information flow isolation in I2C and USB.
Proceedings of the 48th Design Automation Conference, 2011

2010
Theoretical analysis of gate level information flow tracking.
Proceedings of the 47th Design Automation Conference, 2010

2007
Design of an Instruction for Fast and Efficient S-Box Implementation.
Proceedings of the Computational Intelligence and Security, International Conference, 2007


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