Bart Blaner

According to our database1, Bart Blaner authored at least 9 papers between 1992 and 2020.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2020
Data Compression Accelerator on IBM POWER9 and z15 Processors : Industrial Product.
Proceedings of the 47th ACM/IEEE Annual International Symposium on Computer Architecture, 2020

2018
IBM POWER9 opens up a new era of acceleration enablement: OpenCAPI.
IBM J. Res. Dev., 2018

IBM POWER9 processor and system features for computing in the cognitive era.
IBM J. Res. Dev., 2018

2015
CAPI: A Coherent Accelerator Processor Interface.
IBM J. Res. Dev., 2015

The cache and memory subsystems of the IBM POWER8 processor.
IBM J. Res. Dev., 2015

2013
IBM POWER7+ processor on-chip accelerators for cryptography and active memory expansion.
IBM J. Res. Dev., 2013

1994
SCISM: A scalable compound instruction set machine.
IBM J. Res. Dev., 1994

1993
Interlock Collapsing ALU's.
IEEE Trans. Computers, 1993

1992
On the attributes of the SCISM organization.
SIGARCH Comput. Archit. News, 1992


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