Michael S. Floyd

According to our database1, Michael S. Floyd authored at least 28 papers between 2002 and 2021.

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Bibliography

2021

2018
The 24-Core POWER9 Processor With Adaptive Clocking, 25-Gb/s Accelerator Links, and 16-Gb/s PCIe Gen4.
IEEE J. Solid State Circuits, 2018

IBM POWER9 processor and system features for computing in the cognitive era.
IBM J. Res. Dev., 2018

Droop mitigation using critical-path sensors and an on-chip distributed power supply estimation engine in the z14™ enterprise processor.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

2017
3.1 POWER9™: A processor family optimized for cognitive computing with 25Gb/s accelerator links and 16Gb/s PCIe Gen4.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

26.5 Adaptive clocking in the POWER9™ processor for voltage droop protection.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

26.2 Power supply noise in a 22nm z13™ microprocessor.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

2015
Robust power management in the IBM z13.
IBM J. Res. Dev., 2015

Debugging post-silicon fails in the IBM POWER8 bring-up lab.
IBM J. Res. Dev., 2015

Adaptive guardband scheduling to improve system-level efficiency of the POWER7+.
Proceedings of the 48th International Symposium on Microarchitecture, 2015

2013
Active Guardband Management in Power7+ to Save Energy and Maintain Reliability.
IEEE Micro, 2013

Runtime power reduction capability of the IBM POWER7+ chip.
IBM J. Res. Dev., 2013

Virtual Power Management simulation framework for computer systems.
Proceedings of the 2012 IEEE International Symposium on Performance Analysis of Systems & Software, 2013

Single-cycle, pulse-shaped critical path monitor in the POWER7+ microprocessor.
Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED), 2013

2012
Voltage droop reduction using throttling controlled by timing margin feedback.
Proceedings of the Symposium on VLSI Circuits, 2012

Accurate Fine-Grained Processor Power Proxies.
Proceedings of the 45th Annual IEEE/ACM International Symposium on Microarchitecture, 2012

2011
Introducing the Adaptive Energy Management Features of the Power7 Chip.
IEEE Micro, 2011

Adaptive energy-management features of the IBM POWER7 chip.
IBM J. Res. Dev., 2011

Active management of timing guardband to save energy in POWER7.
Proceedings of the 44rd Annual IEEE/ACM International Symposium on Microarchitecture, 2011

2010
Power7: IBM's Next-Generation Server Processor.
IEEE Micro, 2010

Architecting for power management: The IBM POWER7<sup>TM</sup> approach.
Proceedings of the 16th International Conference on High-Performance Computer Architecture (HPCA-16 2010), 2010

Adaptive energy management features of the POWER7TM processor.
Proceedings of the 2010 IEEE Hot Chips 22 Symposium, Stanford, CA, USA, August 22-24, 2010, 2010

2008
Fault-Tolerant Design of the IBM Power6 Microprocessor.
IEEE Micro, 2008

2007
EnergyScale for IBM POWER6 microprocessor-based systems.
IBM J. Res. Dev., 2007

System power management support in the IBM POWER6 microprocessor.
IBM J. Res. Dev., 2007

A Distributed Critical-Path Timing Monitor for a 65nm High-Performance Microprocessor.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

2004

2002
Fault-tolerant design of the IBM pSeries 690 system using POWER4 processor technology.
IBM J. Res. Dev., 2002


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