Ruchir Puri

According to our database1, Ruchir Puri authored at least 86 papers between 1991 and 2020.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Awards

IEEE Fellow

IEEE Fellow 2007, "For contributions to automated logical and physical design of electronic circuits".

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2020
Explainable machine learning in deployment.
Proceedings of the FAT* '20: Conference on Fairness, 2020

2019
The Next Generation of Deep Learning Hardware: Analog Computing.
Proc. IEEE, 2019

Model Agnostic Contrastive Explanations for Structured Data.
CoRR, 2019

NeuNetS: An Automated Synthesis Engine for Neural Network Design.
CoRR, 2019

Bias Mitigation Post-processing for Individual and Group Fairness.
Proceedings of the IEEE International Conference on Acoustics, 2019

2017
Memory-Centric Reconfigurable Accelerator for Classification and Machine Learning Applications.
ACM J. Emerg. Technol. Comput. Syst., 2017

IBM Deep Learning Service.
IBM J. Res. Dev., 2017

IBM Deep Learning Service.
CoRR, 2017

2016
Energy-Efficient Adaptive Hardware Accelerator for Text Mining Application Kernels.
IEEE Trans. Very Large Scale Integr. Syst., 2016

Polynomial Time Algorithm for Area and Power Efficient Adder Synthesis in High-Performance Designs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016

A Proximity Measure using Blink Model.
CoRR, 2016

2015
Analyzing Analytics
Synthesis Lectures on Computer Architecture, Morgan & Claypool Publishers, 2015

PARADIS: An Efficient Parallel Algorithm for In-place Radix Sort.
Proc. VLDB Endow., 2015

Emerging Trends in Design and Applications of Memory-Based Computing and Content-Addressable Memories.
Proc. IEEE, 2015

IBM POWER8 circuit design and energy optimization.
IBM J. Res. Dev., 2015

IBM z13 circuit design and methodology.
IBM J. Res. Dev., 2015


Message from the program chairs.
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2015

2014
Towards Optimal Performance-Area Trade-Off in Adders by Synthesis of Parallel Prefix Structures.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

Circuit and Physical Design of the zEnterprise™ EC12 Microprocessor Chips and Multi-Chip Module.
IEEE J. Solid State Circuits, 2014

5.1 POWER8<sup>TM</sup>: A 12-core server-class processor in 22nm SOI with 7.6Tb/s off-chip bandwidth.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

Bridging high performance and low power in processor design.
Proceedings of the International Symposium on Low Power Electronics and Design, 2014

The POWER8<sup>TM</sup> processor: Designed for big data, analytics, and cloud environments.
Proceedings of the 2014 IEEE International Conference on IC Design & Technology, 2014

Application driven high level design in the era of heterogeneous computing.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2014

Energy-efficient hardware acceleration through computing in the memory.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

POWER8 design methodology innovations for improving productivity and reducing power.
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014

2013
Keynote talk: Opportunities and challenges for high performance microprocessor designs and design automation.
Proceedings of the 26th International Conference on VLSI Design and 12th International Conference on Embedded Systems, 2013


Network flow based datapath bit slicing.
Proceedings of the International Symposium on Physical Design, 2013

Opportunities and challenges for high performance microprocessor designs and design automation.
Proceedings of the International Symposium on Physical Design, 2013

Depth controlled symmetric function fanin tree restructure.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013

LatchPlanner: latch placement algorithm for datapath-oriented high-performance VLSI designs.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013

Intuitive ECO synthesis for high performance circuits.
Proceedings of the Design, Automation and Test in Europe, 2013

2011
Design methodology for the IBM POWER7 microprocessor.
IBM J. Res. Dev., 2011

Design, CAD and technology challenges for future processors: 3D perspectives.
Proceedings of the 48th Design Automation Conference, 2011

2010
The Dawn of 22nm Era: Design and CAD Challenges.
Proceedings of the VLSI Design 2010: 23rd International Conference on VLSI Design, 2010

Logical and physical restructuring of fan-in trees.
Proceedings of the 2010 International Symposium on Physical Design, 2010

Novel binary linear programming for high performance clock mesh synthesis.
Proceedings of the 2010 International Conference on Computer-Aided Design, 2010

EDA challenges and options: investing for the future.
Proceedings of the 47th Design Automation Conference, 2010

History-based VLSI legalization using network flow.
Proceedings of the 47th Design Automation Conference, 2010

2009
Will 22nm be our catch 22!: design and cad challenges.
Proceedings of the 2009 International Symposium on Physical Design, 2009

DeltaSyn: An efficient logic difference optimizer for ECO synthesis.
Proceedings of the 2009 International Conference on Computer-Aided Design, 2009

From milliwatts to megawatts: system level power challenge.
Proceedings of the 46th Design Automation Conference, 2009

Moore's Law: another casualty of the financial meltdown?
Proceedings of the 46th Design Automation Conference, 2009

64-bit prefix adders: Power-efficient topologies and design solutions.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2009

CAD challenges for 3D ICs.
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

2008
Placement-Driven Synthesis Design Closure Tool.
Proceedings of the Handbook of Algorithms for Physical Design Automation., 2008

Fast Dummy-Fill Density Analysis With Coupling Constraints.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

Is Your Layout-Density Verification Exact? - A Fast Exact Deep Submicrometer Density Calculation Algorithm.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

Track Routing and Optimization for Yield.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

Keeping hot chips cool: are IC thermal problems hot air?
Proceedings of the 45th Design Automation Conference, 2008

Custom is from Venus and synthesis from Mars.
Proceedings of the 45th Design Automation Conference, 2008

2007
Dummy fill density analysis with coupling constraints.
Proceedings of the 2007 International Symposium on Physical Design, 2007

Is your layout density verification exact?: a fast exact algorithm for density calculation.
Proceedings of the 2007 International Symposium on Physical Design, 2007

Making Manufacturing Work For You.
Proceedings of the 44th Design Automation Conference, 2007

TROY: Track Router with Yield-driven Wire Planning.
Proceedings of the 44th Design Automation Conference, 2007

Interconnects in the Third Dimension: Design Challenges for 3D ICs.
Proceedings of the 44th Design Automation Conference, 2007

2006
Technology Impacts on Sub-90nm CMOS Circuit Design and Design Methodologies.
Proceedings of the 19th International Conference on VLSI Design (VLSI Design 2006), 2006

Design and CAD challenges in 45nm CMOS and beyond.
Proceedings of the 2006 International Conference on Computer-Aided Design, 2006

Wire density driven global routing for CMP variation and timing.
Proceedings of the 2006 International Conference on Computer-Aided Design, 2006

Gain-based technology mapping for minimum runtime leakage under input vector uncertainty.
Proceedings of the 43rd Design Automation Conference, 2006

2005
Design of sub-90nm Circuits and Design Methodologies.
Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005

Minimizing power with flexible voltage islands.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Keeping hot chips cool.
Proceedings of the 42nd Design Automation Conference, 2005

2004
An Integrated Environment for Technology Closure of Deep-Submicron IC Designs.
IEEE Des. Test Comput., 2004

2003
Design Considerations of Scaled Sub-0.1 ?m PD/SOI CMOS Circuits.
Proceedings of the 4th International Symposium on Quality of Electronic Design (ISQED 2003), 2003

Design and CAD Challenges in sub-90nm CMOS Technologies.
Proceedings of the 2003 International Conference on Computer-Aided Design, 2003

Pushing ASIC performance in a power envelope.
Proceedings of the 40th Design Automation Conference, 2003

2002
Fast and accurate wire delay estimation for physical synthesis of large ASICs.
Proceedings of the 12th ACM Great Lakes Symposium on VLSI 2002, 2002

2000
Combinatorial cell design for CMOS libraries.
Integr., 2000

SOI Digital Circuits: Design Issues.
Proceedings of the 13th International Conference on VLSI Design (VLSI Design 2000), 2000

1999
Hysteresis effect in floating-body partially-depleted SOI CMOS domino circuits.
Proceedings of the 1999 International Symposium on Low Power Electronics and Design, 1999

Optimal P/N width ratio selection for standard cell libraries.
Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999

SOI Digital CMOS VLSI - a Design Perspective.
Proceedings of the 36th Conference on Design Automation, 1999

1998
Design issues in mixed static-domino circuit implementations.
Proceedings of the International Conference on Computer Design: VLSI in Computers and Processors, 1998

1996
A BDD SAT Solver for Satisfiability Testing: An Industrial Case Study.
Ann. Math. Artif. Intell., 1996

Logic optimization by output phase assignment in dynamic logic synthesis.
Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, 1996

1995
Asynchronous circuit synthesis with Boolean satisfiability.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995

1994
A divide-and-conquer approach for asynchronous interface synthesis.
Proceedings of the 7th International Symposium on High Level Synthesis, 1994

Area Efficient Synthesis of Asynchronous Interface Circuits.
Proceedings of the Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1994

A Modular Partitioning Approach for Asynchronous Circuit Synthesis.
Proceedings of the 31st Conference on Design Automation, 1994

1993
Microword length minimization in microprogrammed controller synthesis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993

An efficient algorithm to search for minimal closed covers in sequential machines.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993

Signal Transition Graph Constraints for Speed-independent Ciruit Synthesis.
Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993

1992
An Efficient algorithm for Microword Length Minimization.
Proceedings of the 29th Design Automation Conference, 1992

1991
Searching for a minimal finite state automaton (FSA).
Proceedings of the Third International Conference on Tools for Artificial Intelligence, 1991


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