Bernhard Fechner

According to our database, Bernhard Fechner authored at least 36 papers between 2004 and 2022.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2022

Steganography Hiding Patterns: A Brief Review.

Steffen Wendzel, Luca Caviglione, Bernhard Fechner

Proceedings of the EICC 2022: European Interdisciplinary Cybersecurity Conference, Barcelona, Spain, June 15, 2022

2018

Anforderungsmanagement in großen IT-Projekten.

Kai Engel, Bernhard Fechner, Alicja Berthold-Kraiczy, Andreas Homrighausen, Ruth Dillhage

Inform. Spektrum, 2018

2016

Architectural Support for Fault Tolerance in a Teradevice Dataflow System.

Sebastian Weis, Arne Garbade, Bernhard Fechner, Avi Mendelson, Roberto Giorgi, Theo Ungerer

Int. J. Parallel Program., 2016

2015

Pattern-Based Survey and Categorization of Network Covert Channel Techniques.

Steffen Wendzel, Sebastian Zander, Bernhard Fechner, Christian Herdin

ACM Comput. Surv., 2015

2014

TERAFLUX: Harnessing dataflow in next generation teradevices.

Roberto Giorgi, Rosa M. Badia, François Bodin, Albert Cohen, Paraskevas Evripidou, Paolo Faraboschi, Bernhard Fechner, Guang R. Gao, Arne Garbade, Rahulkumar Gayatri, Sylvain Girbal, Daniel Goodman, Behram Khan, Souad Koliai, Joshua Landwehr, Nhat Minh Lê, Feng Li, Mikel Luján, Avi Mendelson, Laurent Morin, Nacho Navarro, Tomasz Patejko, Antoniu Pop, Pedro Trancoso, Theo Ungerer, Ian Watson, Sebastian Weis, Stéphane Zuckerman, Mateo Valero

Microprocess. Microsystems, 2014

Trust-Enhanced Self-configuration for Organic Computing Systems.

Nizar Msadek, Rolf Kiefhaber, Bernhard Fechner, Theo Ungerer

Proceedings of the Architecture of Computing Systems - ARCS 2014, 2014

2013

Impact of Message Based Fault Detectors on Applications Messages in a Network on Chip.

Arne Garbade, Sebastian Weis, Sebastian Schlingmann, Bernhard Fechner, Theo Ungerer

Proceedings of the 21st Euromicro International Conference on Parallel, 2013

Fault Localization in NoCs Exploiting Periodic Heartbeat Messages in a Many-Core Environment.

Arne Garbade, Sebastian Weis, Sebastian Schlingmann, Bernhard Fechner, Theo Ungerer

Proceedings of the 2013 IEEE International Symposium on Parallel & Distributed Processing, 2013

Fault detection and tolerance mechanisms for future 1000 core systems.

Bernhard Fechner, Arne Garbade, Sebastian Weis, Theo Ungerer

Proceedings of the International Conference on High Performance Computing & Simulation, 2013

The TERAFLUX Project: Exploiting the DataFlow Paradigm in Next Generation Teradevices.

Marco Solinas, Rosa M. Badia, François Bodin, Albert Cohen, Paraskevas Evripidou, Paolo Faraboschi, Bernhard Fechner, Guang R. Gao, Arne Garbade, Sylvain Girbal, Daniel Goodman, Behram Khan, Souad Koliai, Feng Li, Mikel Luján, Laurent Morin, Avi Mendelson, Nacho Navarro, Antoniu Pop, Pedro Trancoso, Theo Ungerer, Mateo Valero, Sebastian Weis, Ian Watson, Stéphane Zuckerman, Roberto Giorgi

Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013

2012

Fast online error detection and correction with thread signature calculae.

Bernhard Fechner

Microprocess. Microsystems, 2012

3, 14159... oder die näherungsweise Berechnung von π.

Bernhard Fechner

Inform. Spektrum, 2012

A multilevel fault model for integrated parallel fault-tolerant systems.

Bernhard Fechner

Concurr. Comput. Pract. Exp., 2012

Fine-grained timing and control flow error checking for hard real-time task execution.

Julian Wolf, Bernhard Fechner, Sascha Uhrig, Theo Ungerer

Proceedings of the 7th IEEE International Symposium on Industrial Embedded Systems, 2012

Fault coverage of a timing and control flow checker for hard real-time systems.

Julian Wolf, Bernhard Fechner, Theo Ungerer

Proceedings of the 18th IEEE International On-Line Testing Symposium, 2012

Challenges for the manycore era: From dawn to dusk(?).

Bernhard Fechner

Proceedings of the 2012 International Conference on High Performance Computing & Simulation, 2012

Fault Localization in NoCs by Timed Heartbeats.

Bernhard Fechner, Arne Garbade, Sebastian Weis, Theo Ungerer

Proceedings of the ARCS 2012 Workshops, 28. Februar - 2. März 2012, München, Germany, 2012

2011

Reliability Bottlenecks in Integrated Parallel Fault-Tolerant Systems.

Bernhard Fechner

Proceedings of the ARCS 2011, 2011

2010

A meta-level true random number generator.

Bernhard Fechner, Andre Osterloh

Int. J. Crit. Comput. Based Syst., 2010

GPU-Based Parallel Signature Scanning and Hash Generation.

Bernhard Fechner

Proceedings of the ARCS '10, 2010

2009

Transiente Fehler in Mikroprozessoren: Mechanismen zur Erkennung, Behebung und Tolerierung.

Bernhard Fechner

Vieweg + Teubner, Germany, ISBN: 978-3-8348-0714-4, 2009

A Tool for Dependable and Distributable Presentations.

Bernhard Fechner, Oliver Körber

Proceedings of the Fourth International Conference on Dependability of Computer Systems, 2009

Fault-Masking Capabilities of Basic Circuit Structures.

Bernhard Fechner

Proceedings of the Fourth International Conference on Dependability of Computer Systems, 2009

2008

Dynamische Fehlererkennungs- und behebungsmechanismen für verlässliche Mikroprozessoren.

Bernhard Fechner

PhD thesis, 2008

Fault-tolerant static scheduling for grids.

Bernhard Fechner, Udo Hönig, Jörg Keller, Wolfram Schiffmann

Proceedings of the 22nd IEEE International Symposium on Parallel and Distributed Processing, 2008

A True Random Number Generator with Built-in Attack Detection.

Bernhard Fechner, Andre Osterloh

Proceedings of the Third International Conference on Dependability of Computer Systems, 2008

2007

Transient Fault Detection in State-Automata.

Bernhard Fechner, Andre Osterloh

Proceedings of the 2007 International Conference on Dependability of Computer Systems (DepCoS-RELCOMEX 2007), 2007

2006

A Result Propagation Scheme for Redundant Multithreaded Systems.

Bernhard Fechner

Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications & Conference on Real-Time Computing Systems and Applications, 2006

A Fault-Tolerant Dynamic Fetch Policy for SMT Processors in Multi-Bus Environments.

Bernhard Fechner

Proceedings of the Fifth International Conference on Parallel Computing in Electrical Engineering (PARELEC 2006), 2006

Web server protection by customized instruction set encoding.

Bernhard Fechner, Jörg Keller, Andreas Wohlfeld

Proceedings of the 20th International Parallel and Distributed Processing Symposium (IPDPS 2006), 2006

Analysis of checksum-based execution schemes for pipelined processors.

Bernhard Fechner

Proceedings of the 20th International Parallel and Distributed Processing Symposium (IPDPS 2006), 2006

Microcode with Embedded Timing Constraints.

Bernhard Fechner

Proceedings of the ARCS 2006, 2006

2005

Dynamic Delay-Fault Injection for Reconfigurable Hardware.

Bernhard Fechner

Proceedings of the 19th International Parallel and Distributed Processing Symposium (IPDPS 2005), 2005

Hardware Reliability.

Irene Eusgeld, Bernhard Fechner, Felix Salfner, Max Walter, Philipp Limbourg, Lijun Zhang

Proceedings of the Dependability Metrics: Advanced Lectures [result from a Dagstuhl seminar, October 30, 2005

2004

A Fault-Tolerant Voting Scheme for Multithreaded Environments.

Bernhard Fechner, Jörg Keller

Proceedings of the 2004 International Conference on Parallel Computing in Electrical Engineering (PARELEC 2004), 2004

Performance Estimation of Virtual Duplex Systems on Simultaneous Multithreaded Processors.

Bernhard Fechner, Jörg Keller, Peter Sobe

Proceedings of the 18th International Parallel and Distributed Processing Symposium (IPDPS 2004), 2004