Mikel Luján

According to our database1, Mikel Luján authored at least 120 papers between 2000 and 2018.

Collaborative distances :
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2018
Cross-Language Interoperability in a Multi-Language Runtime.
ACM Trans. Program. Lang. Syst., 2018

Type Information Elimination from Objects on Architectures with Tagged Pointers Support.
IEEE Trans. Computers, 2018

Fine-Grained Energy Profiling for Deep Convolutional Neural Networks on the Jetson TX1.
CoRR, 2018

Optimising Dynamic Binary Modification Across ARM Microarchitectures.
Proceedings of the 2018 ACM/SPEC International Conference on Performance Engineering, 2018

A CAM-Free Exascalable HPC Router for Low-Energy Communications.
Proceedings of the Architecture of Computing Systems - ARCS 2018, 2018

2017
Fine-grained checkpoint based on non-volatile memory.
Frontiers of IT & EE, 2017

Dealing with under-reported variables: An information theoretic solution.
Int. J. Approx. Reasoning, 2017

A Survey on Optical Network-on-Chip Architectures.
ACM Comput. Surv., 2017

Vectorization of Hybrid Breadth First Search on the Intel Xeon Phi.
CoRR, 2017

Flexible Page-level Memory Access Monitoring Based on Virtualization Hardware.
Proceedings of the 13th ACM SIGPLAN/SIGOPS International Conference on Virtual Execution Environments, 2017

Heterogeneous Managed Runtime Systems: A Computer Vision Case Study.
Proceedings of the 13th ACM SIGPLAN/SIGOPS International Conference on Virtual Execution Environments, 2017

HyperMAMBO-X64: Using Virtualization to Support High-Performance Transparent Binary Translation.
Proceedings of the 13th ACM SIGPLAN/SIGOPS International Conference on Virtual Execution Environments, 2017

Experiences with Building Domain-Specific Compilation Plugins in Graal.
Proceedings of the 14th International Conference on Managed Languages and Runtimes, 2017

Low overhead dynamic binary translation on ARM.
Proceedings of the 38th ACM SIGPLAN Conference on Programming Language Design and Implementation, 2017

MaxSim: A simulation platform for managed applications.
Proceedings of the 2017 IEEE International Symposium on Performance Analysis of Systems and Software, 2017

Fine-grained energy profiling for deep convolutional neural networks on the Jetson TX1.
Proceedings of the 2017 IEEE International Symposium on Workload Characterization, 2017


Designing Low-Power, Low-Latency Networks-on-Chip by Optimally Combining Electrical and Optical Links.
Proceedings of the 2017 IEEE International Symposium on High Performance Computer Architecture, 2017

Subchannel Scheduling for Shared Optical On-chip Buses.
Proceedings of the 25th IEEE Annual Symposium on High-Performance Interconnects, 2017

The Potential of Dynamic Binary Modification and CPU-FPGA SoCs for Simulation.
Proceedings of the 25th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2017


Vectorization of Hybrid Breadth First Search on the Intel Xeon Phi.
Proceedings of the Computing Frontiers Conference, 2017

Designing an exascale interconnect using multi-objective optimization.
Proceedings of the 2017 IEEE Congress on Evolutionary Computation, 2017

Boosting Java Performance Using GPGPUs.
Proceedings of the Architecture of Computing Systems - ARCS 2017, 2017

2016
Compiler-Driven Software Speculation for Thread-Level Parallelism.
ACM Trans. Program. Lang. Syst., 2016

MAMBO: A Low-Overhead Dynamic Binary Modification Tool for ARM.
TACO, 2016

Optimizing Indirect Branches in Dynamic Binary Translators.
TACO, 2016

Purge-Rehab: Eager Software Transactional Memory with High Performance Under Contention.
International Journal of Parallel Programming, 2016

Integrating Transactions into the Data-Driven Multi-threading Model Using the TFlux Platform.
International Journal of Parallel Programming, 2016

A Survey on Design Approaches to Circumvent Permanent Faults in Networks-on-Chip.
ACM Comput. Surv., 2016

Breadth First Search Vectorization on the Intel Xeon Phi.
CoRR, 2016

Towards co-designed optimizations in parallel frameworks: A MapReduce case study.
CoRR, 2016

Cyclic Power-Gating as an Alternative to Voltage and Frequency Scaling.
Computer Architecture Letters, 2016

DReAM: Dynamic Re-arrangement of Address Mapping to Improve the Performance of DRAMs.
Proceedings of the Second International Symposium on Memory Systems, 2016

HAPPY: Hybrid Address-based Page Policy in DRAMs.
Proceedings of the Second International Symposium on Memory Systems, 2016

A partial reconfiguration controller for Altera Stratix V FPGAs.
Proceedings of the 26th International Conference on Field Programmable Logic and Applications, 2016

Parallel Hardware Merge Sorter.
Proceedings of the 24th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2016

Breadth first search vectorization on the Intel Xeon Phi.
Proceedings of the ACM International Conference on Computing Frontiers, CF'16, 2016

Towards co-designed optimizations in parallel frameworks: a MapReduce case study.
Proceedings of the ACM International Conference on Computing Frontiers, CF'16, 2016

Integrating Algorithmic Parameters into Benchmarking and Design Space Exploration in 3D Scene Understanding.
Proceedings of the 2016 International Conference on Parallel Architectures and Compilation, 2016

2015
Architectural support for task scheduling: hardware scheduling for dataflow on NUMA systems.
The Journal of Supercomputing, 2015

Write-Combined Logging: An Optimized Logging for Consistency in NVRAM.
Scientific Programming, 2015

SpiNNaker: Enhanced multicast routing.
Parallel Computing, 2015

HAPPY: Hybrid Address-based Page Policy in DRAMs.
CoRR, 2015

DReAM: Dynamic Re-arrangement of Address Mapping to Improve the Performance of DRAMs.
CoRR, 2015

Boosting Java Performance using GPGPUs.
CoRR, 2015

Objective Assessment of Asthenia using Energy and Low-to-High Spectral Ratio.
Proceedings of the SIGMAP 2015, 2015

Analysis of FPGA and software approaches to simulate unconventional computer architectures.
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2015

CHO: towards a benchmark suite for OpenCL FPGA accelerators.
Proceedings of the 3rd International Workshop on OpenCL, 2015

Introducing SLAMBench, a performance and accuracy benchmarking methodology for SLAM.
Proceedings of the IEEE International Conference on Robotics and Automation, 2015

Amon: An Advanced Mesh-like Optical NoC.
Proceedings of the 23rd IEEE Annual Symposium on High-Performance Interconnects, 2015

Accelerating Interconnect Analysis Using High-Level HDLs and FPGA, SpiNNaker as a Case Study.
Proceedings of the 23rd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2015

Effective Barrier Synchronization on Intel Xeon Phi Coprocessor.
Proceedings of the Euro-Par 2015: Parallel Processing, 2015

Computerised objective measurement of strain in voiced speech.
Proceedings of the 37th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2015

A scalable implementation of information theoretic feature selection for high dimensional data.
Proceedings of the 2015 IEEE International Conference on Big Data, 2015

2014
TERAFLUX: Harnessing dataflow in next generation teradevices.
Microprocessors and Microsystems - Embedded Hardware Design, 2014

Introducing SLAMBench, a performance and accuracy benchmarking methodology for SLAM.
CoRR, 2014

An empirical evaluation of High-Level Synthesis languages and tools for database acceleration.
Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014

On generating multicast routes for SpiNNaker.
Proceedings of the Computing Frontiers Conference, CF'14, 2014

2013
Optimizing software runtime systems for speculative parallelization.
TACO, 2013

SpiNNaker: Fault tolerance in a power- and area- constrained large-scale neuromimetic architecture.
Parallel Computing, 2013

Software transactional memories for Scala.
J. Parallel Distrib. Comput., 2013

A Flexible Memory Controller Supporting Deep Belief Networks with Fixed-Point Arithmetic.
Proceedings of the 2013 IEEE International Symposium on Parallel & Distributed Processing, 2013

Effect of fixed-point arithmetic on deep belief networks (abstract only).
Proceedings of the 2013 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2013

Perceptual Evaluation of Voice Quality and Its Correlation with Acoustic Measurement.
Proceedings of the Seventh UKSim/AMSS European Modelling Symposium, 2013


Exploring sketches for probability estimation with sublinear memory.
Proceedings of the 2013 IEEE International Conference on Big Data, 2013

Empirical Evaluation of Fixed-Point Arithmetic for Deep Belief Networks.
Proceedings of the Reconfigurable Computing: Architectures, Tools and Applications, 2013

2012
Informative Priors for Markov Blanket Discovery.
Proceedings of the Fifteenth International Conference on Artificial Intelligence and Statistics, 2012

Conditional Likelihood Maximisation: A Unifying Framework for Information Theoretic Feature Selection.
Journal of Machine Learning Research, 2012

Managing Burstiness and Scalability in Event-Driven Models on the SpiNNaker Neuromimetic System.
International Journal of Parallel Programming, 2012

Reservation-based Network-on-Chip Timing Models for Large-scale Architectural Simulation.
Proceedings of the 2012 Sixth IEEE/ACM International Symposium on Networks-on-Chip (NoCS), 2012

Architectural Support for Exploiting Fine Grain Parallelism.
Proceedings of the 14th IEEE International Conference on High Performance Computing and Communication & 9th IEEE International Conference on Embedded Software and Systems, 2012

Analytical Assessment of the Suitability of Multicast Communications for the SpiNNaker Neuromimetic System.
Proceedings of the 14th IEEE International Conference on High Performance Computing and Communication & 9th IEEE International Conference on Embedded Software and Systems, 2012

Transactional Access to Shared Memory in StarSs, a Task Based Programming Model.
Proceedings of the Euro-Par 2012 Parallel Processing - 18th International Conference, 2012

Topic 11: Multicore and Manycore Programming.
Proceedings of the Euro-Par 2012 Parallel Processing - 18th International Conference, 2012

SnCTM: reducing false transaction aborts by adaptively changing the source of conflict detection.
Proceedings of the Computing Frontiers Conference, CF'12, 2012

2011
Transaction Reordering to Reduce Aborts in Software Transactional Memory.
Trans. HiPEAC, 2011

Robust Adaptation to Available Parallelism in Transactional Memory Applications.
Trans. HiPEAC, 2011

Event-driven configuration of a neural network CMP system over an homogeneous interconnect fabric.
Parallel Computing, 2011

Garbage collection auto-tuning for Java mapreduce on multi-cores.
Proceedings of the 10th International Symposium on Memory Management, 2011

2010
Fundamental Nano-Patterns to Characterize and Classify Java Methods.
Electr. Notes Theor. Comput. Sci., 2010

Modeling Spiking Neural Networks on SpiNNaker.
Computing in Science and Engineering, 2010

Online Non-stationary Boosting.
Proceedings of the Multiple Classifier Systems, 9th International Workshop, 2010

The economics of garbage collection.
Proceedings of the 9th International Symposium on Memory Management, 2010

Algorithm for Mapping Multilayer BP Networks onto the SpiNNaker Neuromorphic Hardware.
Proceedings of the Ninth International Symposium on Parallel and Distributed Computing, 2010

Clustering JVMs with software transactional memory support.
Proceedings of the 24th IEEE International Symposium on Parallel and Distributed Processing, 2010

Toward a more accurate understanding of the limits of the TLS execution paradigm.
Proceedings of the 2010 IEEE International Symposium on Workload Characterization, 2010

Improving Performance by Reducing Aborts in Hardware Transactional Memory.
Proceedings of the High Performance Embedded Architectures and Compilers, 2010

Scalable Object-Aware Hardware Transactional Memory.
Proceedings of the Euro-Par 2010 - Parallel Processing, 16th International Euro-Par Conference, Ischia, Italy, August 31, 2010

SpiNNaker: impact of traffic locality, causality and burstiness on the performance of the interconnection network.
Proceedings of the 7th Conference on Computing Frontiers, 2010

Efficient parallel implementation of multilayer backpropagation networks on SpiNNaker.
Proceedings of the 7th Conference on Computing Frontiers, 2010

2009
Exploiting object structure in hardware transactional memory.
Comput. Syst. Sci. Eng., 2009

Profiling Transactional Memory Applications.
Proceedings of the 17th Euromicro International Conference on Parallel, 2009

Event-Driven Configuration of a Neural Network CMP System over a Homogeneous Interconnect Fabric.
Proceedings of the Eighth International Symposium on Parallel and Distributed Computing, 2009

On the Performance of Contention Managers for Complex Transactional Memory Benchmarks.
Proceedings of the Eighth International Symposium on Parallel and Distributed Computing, 2009

Understanding the interconnection network of SpiNNaker.
Proceedings of the 23rd international conference on Supercomputing, 2009

Steal-on-Abort: Improving Transactional Memory Performance through Dynamic Transaction Reordering.
Proceedings of the High Performance Embedded Architectures and Compilers, 2009

2008
A first insight into object-aware hardware transactional memory.
Proceedings of the SPAA 2008: Proceedings of the 20th Annual ACM Symposium on Parallelism in Algorithms and Architectures, 2008

Experiences using adaptive concurrency in transactional memory with Lee's routing algorithm.
Proceedings of the 13th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, 2008

Investigating software Transactional Memory on clusters.
Proceedings of the 22nd IEEE International Symposium on Parallel and Distributed Processing, 2008

DiSTM: A Software Transactional Memory Framework for Clusters.
Proceedings of the 2008 International Conference on Parallel Processing, 2008

Adaptive Loop Tiling for a Multi-cluster CMP.
Proceedings of the Algorithms and Architectures for Parallel Processing, 2008

Introducing Aspects to the Implementation of a Java Fork/Join Framework.
Proceedings of the Algorithms and Architectures for Parallel Processing, 2008

Lee-TM: A Non-trivial Benchmark Suite for Transactional Memory.
Proceedings of the Algorithms and Architectures for Parallel Processing, 2008

An Object-Aware Hardware Transactional Memory System.
Proceedings of the 10th IEEE International Conference on High Performance Computing and Communications, 2008

Advanced Concurrency Control for Transactional Memory Using Transaction Commit Rate.
Proceedings of the Euro-Par 2008, 2008

2007
Towards intelligent analysis techniques for object pretenuring.
Proceedings of the 5th International Symposium on Principles and Practice of Programming in Java, 2007

Adaptive performance control for distributed scientific coupled models.
Proceedings of the 21th Annual International Conference on Supercomputing, 2007

Speculative Parallelization - Eliminating the Overhead of Failure.
Proceedings of the High Performance Computing and Communications, 2007

A Study of a Transactional Parallel Routing Algorithm.
Proceedings of the 16th International Conference on Parallel Architecture and Compilation Techniques (PACT 2007), 2007

2006
Performance Evaluation of Storage Formats for Sparse Matrices in Fortran.
Proceedings of the High Performance Computing and Communications, 2006

2005
Elimination of Java array bounds checks in the presence of indirection.
Concurrency - Practice and Experience, 2005

On the conditions necessary for removing abstraction penalties in OOLALA.
Concurrency - Practice and Experience, 2005

Performance control of scientific coupled models in Grid environments.
Concurrency - Practice and Experience, 2005

DIFOJO: A Java Fork/Join Framework for Heterogeneous Networks.
Proceedings of the 13th Euromicro Workshop on Parallel, 2005

Storage Formats for Sparse Matrices in Java.
Proceedings of the Computational Science, 2005

2002
Elimination of Java array bounds checks in the presence of indirection.
Proceedings of the 2002 Joint ACM-ISCOPE Conference on Java Grande 2002, 2002

2000
OoLALA: an object oriented analysis and design of numerical linear algebra.
Proceedings of the 2000 ACM SIGPLAN Conference on Object-Oriented Programming Systems, 2000

Building an object oriented problem solving environment for the parallel numerical solution of PDEs.
Proceedings of the Object Oriented Programming Systems Languages and Applications Conference, 2000


  Loading...