Kyu-Hyoun Kim
Orcid: 0000-0002-5624-8465
According to our database1,
Kyu-Hyoun Kim
authored at least 20 papers
between 1998 and 2024.
Collaborative distances:
Collaborative distances:
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Bibliography
2024
14.1 A Software-Assisted Peak Current Regulation Scheme to Improve Power-Limited Inference Performance in a 5nm AI SoC.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
Proceedings of the International Conference on Electronics, Information, and Communication, 2024
2023
A Switched-Capacitor Integer Compute Unit with Decoupled Storage and Arithmetic for Cloud AI Inference in 5nm CMOS.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023
2022
A 7-nm Four-Core Mixed-Precision AI Chip With 26.2-TFLOPS Hybrid-FP8 Training, 104.9-TOPS INT4 Inference, and Workload-Aware Throttling.
IEEE J. Solid State Circuits, 2022
2021
Proceedings of the IEEE International Solid-State Circuits Conference, 2021
A 7nm 4-Core AI Chip with 25.6TFLOPS Hybrid FP8 Training, 102.4TOPS INT4 Inference and Workload-Aware Throttling.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021
Proceedings of the 48th ACM/IEEE Annual International Symposium on Computer Architecture, 2021
2020
Temperature Aware Adaptations for Improved Read Reliability in STT-MRAM Memory Subsystem.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020
2018
Attaché: Towards Ideal Memory Compression by Mitigating Metadata Bandwidth Overheads.
Proceedings of the 51st Annual IEEE/ACM International Symposium on Microarchitecture, 2018
2017
Contutto: a novel FPGA-based prototyping platform enabling innovation in the memory subsystem of a server class processor.
Proceedings of the 50th Annual IEEE/ACM International Symposium on Microarchitecture, 2017
2013
Proceedings of the 40th Annual International Symposium on Computer Architecture, 2013
2009
A 5.4mW 0.0035mm<sup>2</sup> 0.48psrms-jitter 0.8-to-5GHz non-PLL/DLL all-digital phase generator/rotator in 45nm SOI CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2009
2008
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008
2007
An 8 Gb/s/pin 9.6 ns Row-Cycle 288 Mb Deca-Data Rate SDRAM With an I/O Error Detection Scheme.
IEEE J. Solid State Circuits, 2007
A Second Order Mixed-Mode Charge Pump Scheme for Low Phase/Duty Error and Low Power Consumption.
IEICE Trans. Electron., 2007
2006
A 512-mb DDR3 SDRAM prototype with C<sub>IO</sub> minimization and self-calibration techniques.
IEEE J. Solid State Circuits, 2006
A 20-gb/s 256-mb DRAM with an inductorless quadrature PLL and a cascaded pre-emphasis transmitter.
IEEE J. Solid State Circuits, 2006
An 8Gb/s/pin 9.6ns Row-Cycle 288Mb Deca-Data Rate SDRAM with an I/O Error-Detection Scheme.
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006
1999
IEEE J. Solid State Circuits, 1999
1998
An 8-bit-resolution, 360-μs write time nonvolatile analog memory based on differentially balanced constant-tunneling-current scheme (DBCS).
IEEE J. Solid State Circuits, 1998