Real-Time Scalable Cortical Computing at 46 Giga-Synaptic OPS/Watt with ~100× Speedup in Time-to-Solution and ~100, 000× Reduction in Energy-to-Solution.

[BibT_eX]

[DOI]

Proceedings of the International Conference for High Performance Computing, 2014

2013

Large Payload Streaming Database Sort and Projection on FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 25th International Symposium on Computer Architecture and High Performance Computing, 2013

2012

Efficient in-system RTL verification and debugging using FPGAs (abstract only).

[BibT_eX]

[DOI]

Proceedings of the ACM/SIGDA 20th International Symposium on Field Programmable Gate Arrays, 2012

A cycle-accurate, cycle-reproducible multi-FPGA system for accelerating multi-core processor simulation.

[BibT_eX]

[DOI]

Proceedings of the ACM/SIGDA 20th International Symposium on Field Programmable Gate Arrays, 2012

Database analytics acceleration using FPGAs.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Parallel Architectures and Compilation Techniques, 2012

2011

High-Throughput, Lossless Data Compresion on FPGAs.

[BibT_eX]

[DOI]

Proceedings of the IEEE 19th Annual International Symposium on Field-Programmable Custom Computing Machines, 2011

A 45nm CMOS neuromorphic chip with a scalable architecture for learning in networks of spiking neurons.

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011

1996

Single-chip 4×500-MBd CMOS transceiver.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 1996

Bernard Brezzo

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