Bernard Brezzo

According to our database1, Bernard Brezzo authored at least 11 papers between 1996 and 2015.

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Bibliography

2015
TrueNorth: Design and Tool Flow of a 65 mW 1 Million Neuron Programmable Neurosynaptic Chip.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

A Hardware/Software Approach for Database Query Acceleration with FPGAs.
Int. J. Parallel Program., 2015

2014
Database Analytics: A Reconfigurable-Computing Approach.
IEEE Micro, 2014


2013
Large Payload Streaming Database Sort and Projection on FPGAs.
Proceedings of the 25th International Symposium on Computer Architecture and High Performance Computing, 2013

2012
Efficient in-system RTL verification and debugging using FPGAs (abstract only).
Proceedings of the ACM/SIGDA 20th International Symposium on Field Programmable Gate Arrays, 2012

A cycle-accurate, cycle-reproducible multi-FPGA system for accelerating multi-core processor simulation.
Proceedings of the ACM/SIGDA 20th International Symposium on Field Programmable Gate Arrays, 2012

Database analytics acceleration using FPGAs.
Proceedings of the International Conference on Parallel Architectures and Compilation Techniques, 2012

2011
High-Throughput, Lossless Data Compresion on FPGAs.
Proceedings of the IEEE 19th Annual International Symposium on Field-Programmable Custom Computing Machines, 2011

A 45nm CMOS neuromorphic chip with a scalable architecture for learning in networks of spiking neurons.
Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011

1996
Single-chip 4×500-MBd CMOS transceiver.
IEEE J. Solid State Circuits, 1996


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