Mohit Kapur

Orcid: 0000-0002-2566-8619

According to our database1, Mohit Kapur authored at least 8 papers between 2003 and 2024.

Collaborative distances:

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2024
Towards Generalized On-Chip Communication for Programmable Accelerators in Heterogeneous Architectures.
CoRR, 2024

2023
Janus: An Experimental Reconfigurable SmartNIC with P4 Programmability and SDN Isolation.
Proceedings of the 2023 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2023

2021

2012
Efficient in-system RTL verification and debugging using FPGAs (abstract only).
Proceedings of the ACM/SIGDA 20th International Symposium on Field Programmable Gate Arrays, 2012

A cycle-accurate, cycle-reproducible multi-FPGA system for accelerating multi-core processor simulation.
Proceedings of the ACM/SIGDA 20th International Symposium on Field Programmable Gate Arrays, 2012

2005
10+ gb/s 90-nm CMOS serial link demo in CBGA package.
IEEE J. Solid State Circuits, 2005

2004
10+ Gb/s 90nm CMOS serial link demo in CBGA package.
Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, 2004

2003
45-Gb/s SiGe BiCMOS PRBS generator and PRBS checker [pseudorandom bit sequence].
Proceedings of the IEEE Custom Integrated Circuits Conference, 2003


  Loading...