Won Lee

According to our database1, Won Lee authored at least 9 papers between 1985 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2024
A 4-nm 1.15 TB/s HBM3 Interface With Resistor-Tuned Offset Calibration and In Situ Margin Detection.
IEEE J. Solid State Circuits, January, 2024

2023
A 4nm 1.15TB/s HBM3 Interface with Resistor-Tuned Offset-Calibration and In-Situ Margin-Detection.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023

2022
Networks never rest: An investigation of network evolution in three species of animals.
Soc. Networks, 2022

2019
An 8nm All-Digital 7.3Gb/s/pin LPDDR5 PHY with an Approximate Delay Compensation Scheme.
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019

2016
A 690mV 4.4Gbps/pin all-digital LPDDR4 PHY in 10nm FinFET technology.
Proceedings of the ESSCIRC Conference 2016: 42<sup>nd</sup> European Solid-State Circuits Conference, 2016

2013
All-digital 90° phase-shift DLL with a dithering jitter suppression scheme.
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013

2012
Process Variation Tolerant All-Digital 90° Phase Shift DLL for DDR3 Interface.
IEEE Trans. Circuits Syst. I Regul. Pap., 2012

2010
Process variation tolerant all-digital multiphase DLL for DDR3 interface.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010

1985
A QNAR-AGC estimator with reduced arithmetic complexity.
IEEE Trans. Acoust. Speech Signal Process., 1985


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