YeonGon Cho

According to our database¹, YeonGon Cho authored at least 18 papers between 2012 and 2024.

Collaborative distances:

Dijkstra number² of four.
Erdős number³ of four.

Timeline

Legend:

Book

In proceedings

Article

PhD thesis

Dataset

Other

Links

On csauthors.net:

Bibliography

2024

An LPDDR-based CXL-PNM Platform for TCO-efficient Inference of Transformer-based Large Language Models.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2024

2023

Samsung PIM/PNM for Transfmer Based AI : Energy Efficiency on PIM/PNM Cluster.

[BibT_eX]

[DOI]

Proceedings of the 35th IEEE Hot Chips Symposium, 2023

2022

Near-Memory Processing in Action: Accelerating Personalized Recommendation With AxDIMM.

[BibT_eX]

[DOI]

IEEE Micro, 2022

Aquabolt-XL HBM2-PIM, LPDDR5-PIM With In-Memory Processing, and AXDIMM With Acceleration Buffer.

[BibT_eX]

[DOI]

IEEE Micro, 2022

2021

Aquabolt-XL: Samsung HBM2-PIM with in-memory processing for ML accelerators and beyond.

[BibT_eX]

[DOI]

Proceedings of the IEEE Hot Chips 33 Symposium, 2021

2016

iPAWS: Instruction-issue pattern-based adaptive warp scheduling for GPGPUs.

[BibT_eX]

[DOI]

Proceedings of the 2016 IEEE International Symposium on High Performance Computer Architecture, 2016

2014

ULP-SRP: Ultra Low-Power Samsung Reconfigurable Processor for Biomedical Applications.

[BibT_eX]

[DOI]

ACM Trans. Reconfigurable Technol. Syst., 2014

Seeded region growing on multi-core system.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Consumer Electronics, 2014

Low-power reconfigurable audio processor for mobile devices.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Consumer Electronics, 2014

Improving GPGPU resource utilization through alternative thread block scheduling.

[BibT_eX]

[DOI]

Proceedings of the 20th IEEE International Symposium on High Performance Computer Architecture, 2014

Energy-efficient scheduling for memory-intensive GPGPU workloads.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

2013

Mapping and Scheduling of Tasks and Communications on Many-Core SoC Under Local Memory Constraint.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013

Reliable and energy-efficient 1MHz 0.4V dynamically reconfigurable SoC for ExG applications in 40nm LP CMOS.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

Adaptive compression for instruction code of Coarse Grained Reconfigurable Architectures.

[BibT_eX]

[DOI]

Proceedings of the 2013 International Conference on Field-Programmable Technology, 2013

2012

Design and evaluation of a four-port data cache for high instruction level parallelism reconfigurable processors.

[BibT_eX]

[DOI]

Proceedings of the 30th International IEEE Conference on Computer Design, 2012

Providing cost-effective on-chip network bandwidth in GPGPUs.

[BibT_eX]

[DOI]

Proceedings of the 30th International IEEE Conference on Computer Design, 2012

Efficient code compression for coarse grained reconfigurable architectures.

[BibT_eX]

[DOI]

Moo-Kyoung Chung

Yeon-Gon Cho

Soojung Ryu

Proceedings of the 30th International IEEE Conference on Computer Design, 2012

Implementation of a volume rendering on coarse-grained reconfigurable multiprocessor.

[BibT_eX]

[DOI]

Proceedings of the 2012 International Conference on Field-Programmable Technology, 2012

YeonGon Cho

Timeline

Legend:

Links

On csauthors.net:

Bibliography

Loading...