Pascal Giard

Orcid: 0000-0001-9105-321X

According to our database1, Pascal Giard authored at least 45 papers between 2012 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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Links

On csauthors.net:

Bibliography

2024
Shortened Polar Codes Under Automorphism Ensemble Decoding.
IEEE Commun. Lett., April, 2024

2023
Early-detection scheme based on sequential tests for low-latency communications.
EURASIP J. Wirel. Commun. Netw., December, 2023

Dynamic Frozen-Function Design for Reed-Muller Codes With Automorphism-Based Decoding.
IEEE Commun. Lett., February, 2023

Successive-Cancellation Flip Decoding of Polar Codes with a Simplified Restart Mechanism.
Proceedings of the IEEE Wireless Communications and Networking Conference, 2023

On the Distribution of Partially-Symmetric Codes for Automorphism Ensemble Decoding.
Proceedings of the IEEE Information Theory Workshop, 2023

Unrolled and Pipelined Decoders based on Look-Up Tables for Polar Codes.
Proceedings of the 12th International Symposium on Topics in Coding, 2023

2022
Designing a Pseudorandom Bit Generator With a Novel Five-Dimensional-Hyperchaotic System.
IEEE Trans. Ind. Electron., 2022

2021
Designing a Pseudo-Random Bit Generator with a Novel 5D-Hyperchaotic System.
CoRR, 2021

2020
A Standalone FPGA-Based Miner for Lyra2REv2 Cryptocurrencies.
IEEE Trans. Circuits Syst. I Fundam. Theory Appl., 2020

An Early-Stopping Mechanism for DSCF Decoding of Polar Codes.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2020

2019
FPGA-based Mining of Lyra2REv2 Cryptocurrencies.
CoRR, 2019

Early Detection for Optimal-Latency Communications in Multi-Hop Links.
Proceedings of the 16th International Symposium on Wireless Communication Systems, 2019

A Lyra2 FPGA Core for Lyra2REv2-Based Cryptocurrencies.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

2018
Low-Latency Software Polar Decoders.
J. Signal Process. Syst., 2018

Fast Low-Complexity Decoders for Low-Rate Polar Codes.
J. Signal Process. Syst., 2018

A 9.52 dB NCG FEC Scheme and 162 b/Cycle Low-Complexity Product Decoder Architecture.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018

A Lyra2 FPGA Implementation for Lyra2REv2-Based Cryptocurrencies.
CoRR, 2018

Fast-SSC-flip decoding of polar codes.
Proceedings of the 2018 IEEE Wireless Communications and Networking Conference Workshops, 2018

On the Tradeoff Between Accuracy and Complexity in Blind Detection of Polar Codes.
Proceedings of the 10th IEEE International Symposium on Turbo Codes & Iterative Information Processing, 2018

2017
PolarBear: A 28-nm FD-SOI ASIC for Decoding of Polar Codes.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2017

Comparison of Polar Decoders with Existing Low-Density Parity-Check and Turbo Decoders.
Proceedings of the 2017 IEEE Wireless Communications and Networking Conference Workshops, 2017

Blind detection of polar codes.
Proceedings of the 2017 IEEE International Workshop on Signal Processing Systems, 2017

High-Speed Decoders for Polar Codes
Springer, ISBN: 978-3-319-59781-2, 2017

2016
Flexible and Low-Complexity Encoding and Decoding of Systematic Polar Codes.
IEEE Trans. Commun., 2016

Design of a New Differential Chaos-Shift-Keying System for Continuous Mobility.
IEEE Trans. Commun., 2016

Multi-Mode Unrolled Architectures for Polar Decoders.
IEEE Trans. Circuits Syst. I Regul. Pap., 2016

Fast List Decoders for Polar Codes.
IEEE J. Sel. Areas Commun., 2016

A 9.96 dB NCG FEC scheme and 164 bits/cycle low-complexity product decoder architecture.
CoRR, 2016

Hardware decoders for polar codes: An overview.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Partitioned successive-cancellation list decoding of polar codes.
Proceedings of the 2016 IEEE International Conference on Acoustics, 2016

Stall pattern avoidance in polynomial product codes.
Proceedings of the 2016 IEEE Global Conference on Signal and Information Processing, 2016

A multi-Gbps unrolled hardware list decoder for a systematic polar code.
Proceedings of the 50th Asilomar Conference on Signals, Systems and Computers, 2016

2015
Unrolled Polar Decoders, Part II: Fast List Decoders.
CoRR, 2015

Unrolled Polar Decoders, Part I: Hardware Architectures.
CoRR, 2015

A 638 Mbps low-complexity rate 1/2 polar decoder on FPGAs.
Proceedings of the 2015 IEEE Workshop on Signal Processing Systems, 2015

2014
Fast Polar Decoders: Algorithm and Implementation.
IEEE J. Sel. Areas Commun., 2014

A 237 Gbps Unrolled Hardware Polar Decoder.
CoRR, 2014

Analog network coding for multi-user spread-spectrum communication systems.
Proceedings of the IEEE Wireless Communications and Networking Conference, 2014

Increasing the speed of polar list decoders.
Proceedings of the 2014 IEEE Workshop on Signal Processing Systems, 2014

Fast software polar decoders.
Proceedings of the IEEE International Conference on Acoustics, 2014

Autogenerating software polar decoders.
Proceedings of the 2014 IEEE Global Conference on Signal and Information Processing, 2014

2013
A Fast Software Polar Decoder.
CoRR, 2013

2012
Implementation of a Differential Chaos Shift Keying communication system in GNU radio.
Proceedings of the 2012 International Symposium on Wireless Communication Systems (ISWCS), 2012

FPGA implementation and evaluation of discrete-time chaotic generators circuits.
Proceedings of the 38th Annual Conference on IEEE Industrial Electronics Society, 2012

High-throughput LDPC decoding using the RHS algorithm.
Proceedings of the 2012 Conference on Design and Architectures for Signal and Image Processing, 2012


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