Chau-Chin Huang

According to our database, Chau-Chin Huang authored at least 12 papers between 2013 and 2020.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2020

Clock-Aware Placement for Large-Scale Heterogeneous FPGAs.

Jianli Chen, Zhifeng Lin, Yun-Chih Kuo, Chau-Chin Huang, Yao-Wen Chang, Shih-Chun Chen, Chun-Han Chiang, Sy-Yen Kuo

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Latch Clustering for Timing-Power Co-Optimization.

Chau-Chin Huang, Gustavo E. Téllez, Gi-Joon Nam, Yao-Wen Chang

Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

2018

NTUplace4dr: A Detailed-Routing-Driven Placer for Mixed-Size Circuit Designs With Technology and Region Constraints.

Chau-Chin Huang, Hsin-Ying Lee, Bo-Qiao Lin, Sheng-Wei Yang, Chin-Hao Chang, Szu-To Chen, Yao-Wen Chang, Tung-Chieh Chen, Ismail Bustany

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

End-to-End Industrial Study of Retiming.

Cunxi Yu, Chau-Chin Huang, Gi-Joon Nam, Mihir Choudhury, Victor N. Kravets, Andrew Sullivan, Maciej J. Ciesielski, Giovanni De Micheli

Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018

2017

Clock-aware placement for large-scale heterogeneous FPGAs.

Yun-Chih Kuo, Chau-Chin Huang, Shih-Chun Chen, Chun-Han Chiang, Yao-Wen Chang, Sy-Yen Kuo

Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

Graph-Based Logic Bit Slicing for Datapath-Aware Placement.

Chau-Chin Huang, Bo-Qiao Lin, Hsin-Ying Lee, Yao-Wen Chang, Kuo-Sheng Wu, Jun-Zhi Yang

Proceedings of the 54th Annual Design Automation Conference, 2017

2016

Timing-driven cell placement optimization for early slack histogram compression.

Chau-Chin Huang, Yen-Chun Liu, Yu-Sheng Lu, Yun-Chih Kuo, Yao-Wen Chang, Sy-Yen Kuo

Proceedings of the 53rd Annual Design Automation Conference, 2016

2015

Detailed-Routability-Driven Analytical Placement for Mixed-Size Designs with Technology and Region Constraints.

Chau-Chin Huang, Hsin-Ying Lee, Bo-Qiao Lin, Sheng-Wei Yang, Chin-Hao Chang, Szu-To Chen, Yao-Wen Chang

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015

Detailed-Routing-Driven analytical standard-cell placement.

Chau-Chin Huang, Chien-Hsiung Chiou, Kai-Han Tseng, Yao-Wen Chang

Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

2014

NTUplace4h: A Novel Routability-Driven Placement Algorithm for Hierarchical Mixed-Size Circuit Designs.

Meng-Kai Hsu, Yi-Fang Chen, Chau-Chin Huang, Sheng Chou, Tzu-Hen Lin, Tung-Chieh Chen, Yao-Wen Chang

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

Routability-Driven Blockage-Aware Macro Placement.

Yi-Fang Chen, Chau-Chin Huang, Chien-Hsiung Chiou, Yao-Wen Chang, Chang-Jen Wang

Proceedings of the 51st Annual Design Automation Conference 2014, 2014

2013

Routability-driven placement for hierarchical mixed-size circuit designs.

Meng-Kai Hsu, Yi-Fang Chen, Chau-Chin Huang, Tung-Chieh Chen, Yao-Wen Chang

Proceedings of the 50th Annual Design Automation Conference 2013, 2013