Victor N. Kravets

According to our database1, Victor N. Kravets authored at least 27 papers between 1998 and 2021.

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Bibliography

2021
DATC RDF-2021: Design Flow and Beyond ICCAD Special Session Paper.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021

2020
Symbolic Uniform Sampling with XOR Circuits.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

DATC RDF-2020: Strengthening the Foundation for Academic Research in IC Physical Design.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

Learning to Automate the Design Updates From Observed Engineering Changes in the Chip Development Cycle.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

Engineering Change Order for Combinational and Sequential Design Rectification.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

2019
DATC RDF-2019: Towards a Complete Academic Reference Design Flow.
Proceedings of the International Conference on Computer-Aided Design, 2019

Comprehensive Search for ECO Rectification Using Symbolic Sampling.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

2018
DATC RDF: An Open Design Flow from Logic Synthesis to Detailed Routing.
CoRR, 2018

End-to-End Industrial Study of Retiming.
Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018

DATC RDF: an academic flow from logic synthesis to detailed routing.
Proceedings of the International Conference on Computer-Aided Design, 2018

2017
Sequential engineering change order under retiming and resynthesis.
Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

DATC RDF: Robust design flow database: Invited paper.
Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

Fast-extract with cube hashing.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

2016
OpenDesign flow database: the infrastructure for VLSI design and design automation research.
Proceedings of the 35th International Conference on Computer-Aided Design, 2016

2015
Application of a Key-Value Paradigm to Logic Factoring.
Proc. IEEE, 2015

2014
TACUE: A Timing-Aware Cuts Enumeration Algorithm for Parallel Synthesis.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014

2011
Delay optimization using SOP balancing.
Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

2009
Low cost test point insertion without using extra registers for high performance design.
Proceedings of the 2009 IEEE International Test Conference, 2009

Sequential logic synthesis using symbolic bi-decomposition.
Proceedings of the Design, Automation and Test in Europe, 2009

2008
Merging nodes under sequential observability.
Proceedings of the 45th Design Automation Conference, 2008

2004
Implicit enumeration of structural changes in circuit optimization.
Proceedings of the 41th Design Automation Conference, 2004

2003
Understanding metrics in logic synthesis for routability enhancement.
Proceedings of the 5th International Workshop on System-Level Interconnect Prediction (SLIP 2003), 2003

2002
Resynthesis of multi-level circuits under tight constraints using symbolic optimization.
Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, 2002

2001
Constructive multi-level synthesis by way of functional properties.
PhD thesis, 2001

2000
Generalized Symmetries in Boolean Functions.
Proceedings of the 2000 IEEE/ACM International Conference on Computer-Aided Design, 2000

Constructive Library-Aware Synthesis Using Symmetries.
Proceedings of the 2000 Design, 2000

1998
M32: A Constructive multilevel Logic Synthesis System.
Proceedings of the 35th Conference on Design Automation, 1998


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