Che-Lun Hsu

According to our database, Che-Lun Hsu authored at least 3 papers between 2010 and 2018.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2018

Layout-dependent aging mitigation for critical path timing.

Che-Lun Hsu, Shaofeng Guo, Yibo Lin, Xiaoqing Xu, Meng Li, Runsheng Wang, Ru Huang, David Z. Pan

Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

2015

PARR: pin access planning and regular routing for self-aligned double patterning.

Xiaoqing Xu, Bei Yu, Jhih-Rong Gao, Che-Lun Hsu, David Z. Pan

Proceedings of the 52nd Annual Design Automation Conference, 2015

2010

ESD protection circuit for high-voltage CMOS ICs with improved immunity against transient-induced latchup.

Ming-Dou Ker, Che-Lun Hsu, Wen-Yi Chen

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010