Yun-Chao You

According to our database1, Yun-Chao You authored at least 4 papers between 2010 and 2014.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of five.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
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Links

On csauthors.net:

Bibliography

2014
BIST-Assisted Tuning Scheme for Minimizing IO-Channel Power of TSV-Based 3D DRAMs.
Proceedings of the 23rd IEEE Asian Test Symposium, 2014

2013
A hybrid ECC and redundancy technique for reducing refresh power of DRAMs.
Proceedings of the 31st IEEE VLSI Test Symposium, 2013

2012
A built-in self-test scheme for 3D RAMs.
Proceedings of the 2012 IEEE International Test Conference, 2012

2010
Enhanced IEEE 1500 test wrapper for testing small RAMs in SOCs.
Proceedings of the Annual IEEE International SoC Conference, SoCC 2010, 2010


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