Cheng Wang

Affiliations:
  • Intel Corporation, Programming Systems Lab, Santa Clara, CA, USA


According to our database1, Cheng Wang authored at least 19 papers between 2005 and 2014.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2014
Just-In-Time Software Pipelining.
Proceedings of the 12th Annual IEEE/ACM International Symposium on Code Generation and Optimization, 2014

2013
Allocating rotating registers by scheduling.
Proceedings of the 46th Annual IEEE/ACM International Symposium on Microarchitecture, 2013

Acceldroid: Co-designed acceleration of Android bytecode.
Proceedings of the 2013 IEEE/ACM International Symposium on Code Generation and Optimization, 2013

TSO_ATOMICITY: efficient hardware primitive for TSO-preserving region optimizations.
Proceedings of the Architectural Support for Programming Languages and Operating Systems, 2013

2012
From Locks to Correct and Efficient Transactional Memory.
J. Circuits Syst. Comput., 2012

SMARQ: Software-Managed Alias Register Queue for Dynamic Optimizations.
Proceedings of the 45th Annual IEEE/ACM International Symposium on Microarchitecture, 2012

2011
A HW/SW co-designed heterogeneous multi-core virtual machine for energy-efficient general purpose computing.
Proceedings of the CGO 2011, 2011

LAR-CC: Large atomic regions with conditional commits.
Proceedings of the CGO 2011, 2011

Modeling and Performance Evaluation of TSO-Preserving Binary Optimization.
Proceedings of the 2011 International Conference on Parallel Architectures and Compilation Techniques, 2011

2010
TAO: two-level atomicity for dynamic binary optimizations.
Proceedings of the CGO 2010, 2010

2009
Dynamic parallelization of single-threaded binary programs using speculative slicing.
Proceedings of the 23rd international conference on Supercomputing, 2009

2008
Supporting Legacy Binary Code in a Software Transaction Compiler with Dynamic Binary Translation and Optimization.
Proceedings of the Compiler Construction, 17th International Conference, 2008

2007
Compiler-Managed Software-based Redundant Multi-Threading for Transient Fault Detection.
Proceedings of the Fifth International Symposium on Code Generation and Optimization (CGO 2007), 2007

Code Generation and Optimization for Transactional Memory Constructs in an Unmanaged Language.
Proceedings of the Fifth International Symposium on Code Generation and Optimization (CGO 2007), 2007

StarDBT: An Efficient Multi-platform Dynamic Binary Translation System.
Proceedings of the Advances in Computer Systems Architecture, 2007

2006
LIFT: A Low-Overhead Practical Information Flow Tracking System for Detecting Security Attacks.
Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-39 2006), 2006

Software-Based Transparent and Comprehensive Control-Flow Error Detection.
Proceedings of the Fourth IEEE/ACM International Symposium on Code Generation and Optimization (CGO 2006), 2006

Selective Runtime Memory Disambiguation in a Dynamic Binary Translator.
Proceedings of the Compiler Construction, 15th International Conference, 2006

2005
Dynamic binary control-flow errors detection.
SIGARCH Comput. Archit. News, 2005


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