Shiliang Hu

According to our database1, Shiliang Hu authored at least 13 papers between 2004 and 2017.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2017
TMI: thread memory isolation for false sharing repair.
Proceedings of the 50th Annual IEEE/ACM International Symposium on Microarchitecture, 2017

A transfer learning approach for classification of clinical significant prostate cancers from mpMRI scans.
Proceedings of the Medical Imaging 2017: Computer-Aided Diagnosis, 2017

2016
Remix: online detection and repair of cache contention for the JVM.
Proceedings of the 37th ACM SIGPLAN Conference on Programming Language Design and Implementation, 2016

LASER: Light, Accurate Sharing dEtection and Repair.
Proceedings of the 2016 IEEE International Symposium on High Performance Computer Architecture, 2016

2013
QuickRec: prototyping an intel architecture extension for record and replay of multithreaded programs.
Proceedings of the 40th Annual International Symposium on Computer Architecture, 2013

2011
CoreRacer: a practical memory race recorder for multicore x86 TSO processors.
Proceedings of the 44rd Annual IEEE/ACM International Symposium on Microarchitecture, 2011

A HW/SW co-designed heterogeneous multi-core virtual machine for energy-efficient general purpose computing.
Proceedings of the CGO 2011, 2011

2010
TAO: two-level atomicity for dynamic binary optimizations.
Proceedings of the CGO 2010, 2010

2009
Dynamic parallelization of single-threaded binary programs using speculative slicing.
Proceedings of the 23rd international conference on Supercomputing, 2009

2007
StarDBT: An Efficient Multi-platform Dynamic Binary Translation System.
Proceedings of the Advances in Computer Systems Architecture, 2007

2006
Reducing Startup Time in Co-Designed Virtual Machines.
Proceedings of the 33rd International Symposium on Computer Architecture (ISCA 2006), 2006

An approach for implementing efficient superscalar CISC processors.
Proceedings of the 12th International Symposium on High-Performance Computer Architecture, 2006

2004
Using Dynamic Binary Translation to Fuse Dependent Instructions.
Proceedings of the 2nd IEEE / ACM International Symposium on Code Generation and Optimization (CGO 2004), 2004


  Loading...