We stand with Ukraine

We stand with Ukraine

Chenlei Fang

Orcid: 0000-0002-0518-6348

According to our database¹, Chenlei Fang authored at least 19 papers between 2014 and 2023.

Collaborative distances:

Dijkstra number² of four.
Erdős number³ of three.

Timeline

Legend:

Book

In proceedings

Article

PhD thesis

Dataset

Other

Links

On csauthors.net:

Bibliography

2023

Efficient Test Chip Design via Smart Computation.

[BibT_eX]

[DOI]

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Ronald D. Blanton

ACM Trans. Design Autom. Electr. Syst., March, 2023

2021

Memory-Efficient Adaptive Test Pattern Reordering for Accurate Diagnosis.

[BibT_eX]

[DOI]

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R. D. Shawn Blanton

Proceedings of the 39th IEEE VLSI Test Symposium, 2021

2020

Towards Smarter Diagnosis: A Learning-based Diagnostic Outcome Previewer.

[BibT_eX]

[DOI]

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R. D. (Shawn) Blanton

ACM Trans. Design Autom. Electr. Syst., 2020

Knowledge Transfer for Diagnosis Outcome Preview with Limited Data.

[BibT_eX]

[DOI]

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R. D. Shawn Blanton

Proceedings of the IEEE International Test Conference, 2020

LAIDAR: Learning for Accuracy and Ideal Diagnostic Resolution.

[BibT_eX]

[DOI]

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R. D. Shawn Blanton

Proceedings of the IEEE International Test Conference, 2020

Diagnosis Outcome Prediction on Limited Data via Transferred Random Forest.

[BibT_eX]

[DOI]

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R. D. Shawn Blanton

Proceedings of the IEEE International Test Conference in Asia, 2020

Adaptive Test Pattern Reordering for Diagnosis using k-Nearest Neighbors.

[BibT_eX]

[DOI]

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R. D. Shawn Blanton

Proceedings of the IEEE International Test Conference in Asia, 2020

2019

Diagnosis Outcome Preview through Learning.

[BibT_eX]

[DOI]

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R. D. Shawn Blanton

Proceedings of the 37th IEEE VLSI Test Symposium, 2019

Improving Test Chip Design Efficiency via Machine Learning.

[BibT_eX]

[DOI]

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R. D. (Shawn) Blanton

Proceedings of the IEEE International Test Conference, 2019

IPSA: Integer Programming via Sparse Approximation for Efficient Test-Chip Design.

[BibT_eX]

[DOI]

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R. D. Shawn Blanton

Proceedings of the 37th IEEE International Conference on Computer Design, 2019

2018

Improving Diagnosis Efficiency via Machine Learning.

[BibT_eX]

[DOI]

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R. D. Shawn Blanton

Proceedings of the IEEE International Test Conference, 2018

2016

An aggregating based model order reduction method for power grids.

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Integr., 2016

High-speed link verification based on statistical inference.

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Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Efficient performance modeling via Dual-Prior Bayesian Model Fusion for analog and mixed-signal circuits.

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Proceedings of the 53rd Annual Design Automation Conference, 2016

Efficient performance modeling of analog integrated circuits via kernel density based sparse regression.

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Proceedings of the 53rd Annual Design Automation Conference, 2016

2015

Efficient bit error rate estimation for high-speed link by Bayesian model fusion.

[BibT_eX]

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Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Efficient multivariate moment estimation via Bayesian model fusion for analog and mixed-signal circuits.

[BibT_eX]

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Proceedings of the 52nd Annual Design Automation Conference, 2015

PGMOR: An Efficient Model Order Reduction Method for Power Grids.

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Proceedings of the 14th International Conference on Computer-Aided Design and Computer Graphics, 2015

2014

BMF-BD: Bayesian Model Fusion on Bernoulli Distribution for Efficient Yield Estimation of Integrated Circuits.

[BibT_eX]

[DOI]

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Proceedings of the 51st Annual Design Automation Conference 2014, 2014

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