Wei Cai
Orcid: 0000-0002-7622-4532Affiliations:
- University of North Carolina, Department of Mathematics, Charlotte, NC, USA (since 1989)
- Southern Methodist University, Department of Mathematics, Dallas, TX, USA
- University of California at Santa Barbara, Department of Mathematics, CA, USA (1994 - 1996)
- Brown University, Providence, RI, USA (PhD 1989)
According to our database1,
Wei Cai
authored at least 24 papers
between 2003 and 2023.
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Bibliography
2023
A path integral Monte Carlo (PIMC) method based on Feynman-Kac formula for electrical impedance tomography.
J. Comput. Phys., March, 2023
2022
A Parallel Iterative Probabilistic Method for Mixed Problems of Laplace Equations with the Feynman-Kac Formula of Killed Brownian Motions.
SIAM J. Sci. Comput., October, 2022
FBSDE based neural network algorithms for high-dimensional quasilinear parabolic PDEs.
J. Comput. Phys., 2022
2020
J. Comput. Phys., 2020
2018
Efficient Yield Optimization for Analog and SRAM Circuits via Gaussian Process Regression and Adaptive Yield Estimation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018
2017
Discovering variable fractional orders of advection-dispersion equations from field data using multi-fidelity Bayesian optimization.
J. Comput. Phys., 2017
Efficient two-dimensional simulations of the fractional Szabo equation with different time-stepping schemes.
Comput. Math. Appl., 2017
2016
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
2013
A Parallel Method for Solving Laplace Equations with Dirichlet Data Using Local Boundary Integral Equations and Random Walks.
SIAM J. Sci. Comput., 2013
2010
NHAR: A non-homogeneous Arnoldi method for fast simulation of RCL circuits with a large number of ports.
Int. J. Circuit Theory Appl., 2010
Stochastic Sparse-Grid Collocation Algorithm for Steady-State Analysis of Nonlinear System with Process Variations.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010
2009
Generalized Stochastic Collocation Method for Variation-Aware Capacitance Extraction of Interconnects Considering Arbitrary Random Probability.
IEICE Trans. Electron., 2009
A Modified Nested Sparse Grid Based Adaptive Stochastic Collocation Method for Statistical Static Timing Analysis.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009
Intra-Die Spatial Correlation Extraction with Maximum Likelihood Estimation Method for Multiple Test Chips.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009
2008
Adaptive Stochastic Collocation Method for Parameterized Statistical Timing Analysis with Quadratic Delay Model.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008
Adaptive Stochastic Collocation Method (ASCM) for Parameterized Statistical Timing Analysis with Quadratic Delay Model.
Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008
Timing yield driven clock skew scheduling considering non-Gaussian distributions of critical path delays.
Proceedings of the 45th Design Automation Conference, 2008
2007
A sparse grid based spectral stochastic collocation method for variations-aware capacitance extraction of interconnects under nanometer process technology.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007
Stochastic Sparse-grid Collocation Algorithm (SSCA) for Periodic Steady-State Analysis of Nonlinear System with Process Variations.
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007
2006
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
Proceedings of the Conference on Design, Automation and Test in Europe, 2006
A Spectral Stochastic Collocation Method for Capacitance Extraction of Interconnects with Process Variations.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006
2004
Frequency domain wavelet method with GMRES for large-scale linear circuit simulation.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
2003
Behavioral modeling for analog system-level simulation by wavelet collocation method.
IEEE Trans. Circuits Syst. II Express Briefs, 2003