Weiping Shi

Affiliations:
  • Texas A&M University, College Station, Texas, USA


According to our database1, Weiping Shi authored at least 108 papers between 1989 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of two.

Awards

IEEE Fellow

IEEE Fellow 2017, "For contributions to modeling and design of VLSI interconnects".

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

Online presence:

On csauthors.net:

Bibliography

2023
Beamforming design for RIS-aided amplify-and-forward relay networks.
Frontiers Inf. Technol. Electron. Eng., December, 2023

Enhanced-Rate Iterative Beamformers for Active IRS-Assisted Wireless Communications.
IEEE Wirel. Commun. Lett., September, 2023

An Explicit-Correction-Force Scheme of IB-LBM Based on Interpolated Particle Distribution Function.
Entropy, March, 2023

Power Allocation for IRS-Aided Two-Way Decode-and-Forward Relay Wireless Network.
IEEE Trans. Veh. Technol., 2023

STAR-RIS-UAV Aided Coordinated Multipoint Cellular System for Multi-user Networks.
CoRR, 2023

Beamforming Design for RIS-Aided AF Relay Networks.
CoRR, 2023

Precoding and Beamforming Design for Intelligent Reconfigurable Surface-Aided Hybrid Secure Spatial Modulation.
CoRR, 2023

A Non-Equilibrium Interpolation Scheme for IB-LBM Optimized by Approximate Force.
Axioms, 2023

2022
Intelligent Reflecting Surface Aided Secure Transmission With Colluding Eavesdroppers.
IEEE Trans. Veh. Technol., 2022

High-Performance Estimation of Jamming Covariance Matrix for IRS-Aided Directional Modulation Network With a Malicious Attacker.
IEEE Trans. Veh. Technol., 2022

Communication-Efficient Coordinated RSS-Based Distributed Passive Localization via Drone Cluster.
IEEE Trans. Veh. Technol., 2022

Beamforming Design for IRS-Aided Decode-and-Forward Relay Wireless Network.
IEEE Trans. Green Commun. Netw., 2022

Secrecy Throughput Maximization for IRS-Aided MIMO Wireless Powered Communication Networks.
IEEE Trans. Commun., 2022

Joint Optimization for RIS-Assisted Wireless Communications: From Physical and Electromagnetic Perspectives.
IEEE Trans. Commun., 2022

Beamforming and Transmit Power Design for Intelligent Reconfigurable Surface-Aided Secure Spatial Modulation.
IEEE J. Sel. Top. Signal Process., 2022

2021
Enhanced Secrecy Rate Maximization for Directional Modulation Networks via IRS.
IEEE Trans. Commun., 2021

Enhanced Secure Wireless Information and Power Transfer via Intelligent Reflecting Surface.
IEEE Commun. Lett., 2021

Physical Layer Security Techniques for Future Wireless Networks.
CoRR, 2021

Beamforming and Transmit Power Design for Intelligent Reconfigurable Surface-aided Secure Spatial Modulation.
CoRR, 2021

An Efficient Network Solver for Dynamic Simulation of Power Systems Based on Hierarchical Inverse Computation and Modification.
CoRR, 2021

Global Optimization for IRS-Assisted Wireless Communications: from Physics and Electromagnetic Perspectives.
CoRR, 2021

2020
Layout Capacitance Extraction Using Automatic Pre-Characterization and Machine Learning.
Proceedings of the 21st International Symposium on Quality Electronic Design, 2020

2019
Fast supervised novelty detection and its application in remote sensing.
Soft Comput., 2019

Accurate and efficient estimation of small P-values with the cross-entropy method: applications in genomic data analysis.
Bioinform., 2019

Fast Electromagnetic Transient Simulation Based on Hierarchical Low-Rank Approximation.
Proceedings of the IEEE Power & Energy Society Innovative Smart Grid Technologies Conference, 2019

2018
Capacitance Extraction With Provably Good Absorbing Boundary Conditions.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

2016
Research on the DFT of ZC Sequence in TD-LTE System.
Wirel. Pers. Commun., 2016

Macro Model of Advanced Devices for Parasitic Extraction.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016

A lattice Boltzmann model for the generalized Boussinesq equation.
Appl. Math. Comput., 2016

High-speed link verification based on statistical inference.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Fast compressive sensing reconstruction algorithm on FPGA using Orthogonal Matching Pursuit.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

2013
Low-Complexity Carrier Frequency Offset Estimation Algorithm in TD-LTE.
J. Networks, 2013

2012
$O(mn)$ Time Algorithm for Optimal Buffer Insertion of Nets With $m$ Sinks.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

2011
Numerical simulation of viscous flow over non-smooth surfaces.
Comput. Math. Appl., 2011

Lagrangian relaxation for gate implementation selection.
Proceedings of the 2011 International Symposium on Physical Design, 2011

2010
Ultra-fast interconnect driven cell cloning for minimizing critical path delay.
Proceedings of the 2010 International Symposium on Physical Design, 2010

2009
Inductance Extraction for Interconnects in the Presence of Nonlinear Magnetic Materials.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009

The impact of BEOL lithography effects on the SRAM cell performance and yield.
Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009

Fast characterization of parameterized cell library.
Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009

2008
A Preconditioned Hierarchical Algorithm for Impedance Extraction of Three-Dimensional Structures With Multiple Dielectrics.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

Buffering Interconnect for Multicore Processor Designs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

Efficient, scalable hardware engine for Boolean satisfiability and unsatisfiable core extraction.
IET Comput. Digit. Tech., 2008

Multi-scenario buffer insertion in multi-core processor designs.
Proceedings of the 2008 International Symposium on Physical Design, 2008

SRAM methodology for yield and power efficiency: per-element selectable supplies and memory reconfiguration schemes.
Proceedings of the 2008 International Symposium on Low Power Electronics and Design, 2008

Circuit-wise buffer insertion and gate sizing algorithm with scalability.
Proceedings of the 45th Design Automation Conference, 2008

2007
Path-Based Buffer Insertion.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

Wire Sizing for Non-Tree Topology.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

Fast Algorithms for Slew-Constrained Minimum Cost Buffering.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

An O(bn^2) Time Algorithm for Optimal Buffer Insertion with b Buffer Types
CoRR, 2007

Probabilistic Congestion Prediction with Partial Blockages.
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007

An Efficient Algorithm for RLC Buffer Insertion.
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007

Impedance extraction for 3-D structures with multiple dielectrics using preconditioned boundary element method.
Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

Fast Capacitance Extraction in Multilayer, Conformal and Embedded Dielectric using Hybrid Boundary Element Method.
Proceedings of the 44th Design Automation Conference, 2007

A New Twisted Differential Line Structure in Global Bus Design.
Proceedings of the 44th Design Automation Conference, 2007

A New Methodology for Interconnect Parasitics Extraction Considering Photo-Lithography Effects.
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

2006
Fast 3-D Capacitance Extraction by Inexact Factorization and Reduction.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

An O(bn<sup>2</sup>) time algorithm for optimal buffer insertion with b buffer types.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

An Efficient, Scalable Hardware Engine for Boolean SATisfiability.
Proceedings of the 24th International Conference on Computer Design (ICCD 2006), 2006

A new RLC buffer insertion algorithm.
Proceedings of the 2006 International Conference on Computer-Aided Design, 2006

Buffer insertion in large circuits with constructive solution search techniques.
Proceedings of the 43rd Design Automation Conference, 2006

Model order reduction of linear networks with massive ports via frequency-dependent port packing.
Proceedings of the 43rd Design Automation Conference, 2006

An <i>O</i>(<i>mn</i>) time algorithm for optimal buffer insertion of nets with <i>m</i> sinks.
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

2005
Sparse transformations and preconditioners for 3-D capacitance extraction.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005

A fast algorithm for optimal buffer insertion.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005

Longest-path selection for delay test under process variation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005

The Rectilinear Steiner Arborescence Problem Is NP-Complete.
SIAM J. Comput., 2005

Static Compaction of Delay Tests Considering Power Supply Noise.
Proceedings of the 23rd IEEE VLSI Test Symposium (VTS 2005), 2005

A vector-based approach for power supply noise analysis in test compaction.
Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005

An optimal test pattern selection method to improve the defect coverage.
Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005

Making fast buffer insertion even faster via approximation techniques.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004
A divide-and-conquer algorithm for 3-D capacitance extraction.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004

A Statistical Fault Coverage Metric for Realistic Path Delay Faults.
Proceedings of the 22nd IEEE VLSI Test Symposium (VTS 2004), 2004

Minimum moment Steiner trees.
Proceedings of the Fifteenth Annual ACM-SIAM Symposium on Discrete Algorithms, 2004

A Circuit Level Fault Model for Resistive Shorts of MOS Gate Oxide.
Proceedings of the Fifth International Workshop on Microprocessor Test and Verification (MTV 2004), 2004

K Longest Paths Per Gate (KLPG) Test Generation for Scan-Based Sequential Circuits.
Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

A Divide-and-Conquer Algorithm for 3D Capacitance Extraction.
Proceedings of the 5th International Symposium on Quality of Electronic Design (ISQED 2004), 2004

PARADE: PARAmetric Delay Evaluation under Process Variation.
Proceedings of the 5th International Symposium on Quality of Electronic Design (ISQED 2004), 2004

Sparse transformations and preconditioners for hierarchical 3-D capacitance extraction with multiple dielectrics.
Proceedings of the 41th Design Automation Conference, 2004

Complexity analysis and speedup techniques for optimal buffer insertion with minimum cost.
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

2003
A circuit level fault model for resistive bridges.
ACM Trans. Design Autom. Electr. Syst., 2003

A Circuit Level Fault Model for Resistive Opens and Bridges.
Proceedings of the 21st IEEE VLSI Test Symposium (VTS 2003), 27 April, 2003

Process variation dimension reduction based on SVD.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

CodSim -- A Combined Delay Fault Simulator.
Proceedings of the 18th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2003), 2003

An O(nlogn) time algorithm for optimal buffer insertion.
Proceedings of the 40th Design Automation Conference, 2003

The clinical evaluation of the modern technology of computer in echocardiography.
Proceedings of the CARS 2003. Computer Assisted Radiology and Surgery. Proceedings of the 17th International Congress and Exhibition, 2003

Minimizing Defective Part Level Using a Linear Programming-Based Optimal Test Selection Method.
Proceedings of the 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, 2003

Improving boundary element methods for parasitic extraction.
Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

2002
A fast hierarchical algorithm for three-dimensional capacitanceextraction.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002

Fast Inductance Extraction of Large VLSI Circuits.
Proceedings of the 16th International Parallel and Distributed Processing Symposium (IPDPS 2002), 2002

A solenoidal basis method for efficient inductance extraction.
Proceedings of the 39th Design Automation Conference, 2002

2001
Structural Diagnosis of Wiring Networks: Finding Connected Components of Unknown Subgraphs.
SIAM J. Discret. Math., 2001

2000
On Crossing Sets, Disjoint Sets, and Pagenumber.
J. Algorithms, 2000

1999
Diagnosis of Wiring Networks: An Optimal Randomized Algorithm for Finding Connected Components of Unknown Graphs.
SIAM J. Comput., 1999

1998
A Fast Hierarchical Algorithm for 3-D Capacitance Extraction.
Proceedings of the 35th Conference on Design Automation, 1998

1997
Optimal Structural Diagnosis of Wiring Networks.
Proceedings of the Digest of Papers: FTCS-27, 1997

1996
A fast algorithm for area minimization of slicing floorplans.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996

Harvest Rate of Reconfigurable Pipelines.
IEEE Trans. Computers, 1996

Area Minimization for Hierarchical Floorplans.
Algorithmica, 1996

Efficient Deterministic Algorithms for Embedding Graphs on Books.
Proceedings of the Computing and Combinatorics, Second Annual International Conference, 1996

1995
Optimal interconnect diagnosis of wiring networks.
IEEE Trans. Very Large Scale Integr. Syst., 1995

An optimal algorithm for area minimization of slicing floorplans.
Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, 1995

Optimal Algorithms for Finding Connected Components of an Unknown Graph.
Proceedings of the Computing and Combinatorics, First Annual International Conference, 1995

1994
A General Method to Design and Reconfigure Loop-Based Linear Arrays.
Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems, 1994

1992
Probabilistic analysis and algorithms for reconfiguration of memory arrays.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1992

Single Tree Grammars.
Proceedings of the Theoretical Studies in Computer Science, 1992

1991
An O(n log² h) Time Algorithm for the Three-Dimensional Convex Hull Problem.
SIAM J. Comput., 1991

1990
Optimal Diagnosis Procedures for k-out-of-n Structures.
IEEE Trans. Computers, 1990

1989
Optimal wafer probe testing and diagnosis of k-out-of-n structures.
Proceedings of the 1989 IEEE International Conference on Computer-Aided Design, 1989


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