Chi-Keung Luk

According to our database1, Chi-Keung Luk authored at least 27 papers between 1993 and 2018.

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Bibliography

2018
Performance Characterisation and Simulation of Intel's Integrated GPU Architecture.
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2018

2015
Fast Computational GPU Design with GT-Pin.
Proceedings of the 2015 IEEE International Symposium on Workload Characterization, 2015

2013
SD3: An Efficient Dynamic Data-Dependence Profiling Mechanism.
IEEE Trans. Computers, 2013

2011
A Synergetic Approach to Throughput Computing on x86-Based Multicore Desktops.
IEEE Softw., 2011

The pochoir stencil compiler.
Proceedings of the SPAA 2011: Proceedings of the 23rd Annual ACM Symposium on Parallelism in Algorithms and Architectures, 2011

2010
Analyzing Parallel Programs with Pin.
Computer, 2010

SD3: A Scalable Approach to Dynamic Data-Dependence Profiling.
Proceedings of the 43rd Annual IEEE/ACM International Symposium on Microarchitecture, 2010

2009
Qilin: exploiting parallelism on heterogeneous multiprocessors with adaptive mapping.
Proceedings of the 42st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-42 2009), 2009

2007
PinOS: a programmable framework for whole-system dynamic instrumentation.
Proceedings of the 3rd International Conference on Virtual Execution Environments, 2007

2005
Controlling program execution through binary instrumentation.
SIGARCH Comput. Archit. News, 2005

Pin: building customized program analysis tools with dynamic instrumentation.
Proceedings of the ACM SIGPLAN 2005 Conference on Programming Language Design and Implementation, 2005

2004
Ispike: A Post-link Optimizer for the Intel®Itanium®Architecture.
Proceedings of the 2nd IEEE / ACM International Symposium on Code Generation and Optimization (CGO 2004), 2004

2002
Asim: A Performance Model Framework.
Computer, 2002

Profile-guided post-link stride prefetching.
Proceedings of the 16th international conference on Supercomputing, 2002

2001
Architectural and compiler support for effective instruction prefetching: a cooperative approach.
ACM Trans. Comput. Syst., 2001

Tolerating memory latency through software-controlled pre-execution in simultaneous multithreading processors.
Proceedings of the 28th Annual International Symposium on Computer Architecture, 2001

2000
Optimizing the cache performance of non-numeric applications.
PhD thesis, 2000

Understanding Why Correlation Profiling Improves the Predictability of Data Cache Misses in Nonnumeric Applications.
IEEE Trans. Computers, 2000

1999
Automatic Compiler-Inserted Prefetching for Pointer-Based Applications.
IEEE Trans. Computers, 1999

Memory Forwarding: Enabling Aggressive Layout Optimizations by Guaranteeing the Safety of Data Relocation.
Proceedings of the 26th Annual International Symposium on Computer Architecture, 1999

1998
Cooperative Prefetching: Compiler and Hardware Support for Effective Instruction Prefetching in Modern Processors.
Proceedings of the 31st Annual IEEE/ACM International Symposium on Microarchitecture, 1998

1997
Predicting Data Cache Misses in Non-Numeric Applications through Correlation Profiling.
Proceedings of the Thirtieth Annual IEEE/ACM International Symposium on Microarchitecture, 1997

1996
Compiler-Based Prefetching for Recursive Data Structures.
Proceedings of the ASPLOS-VII Proceedings, 1996

1995
A survey of languages integrating functional, object-oriented and logic programming.
Microprocess. Microprogramming, 1995

I+: A Multiparadigm Language for Object-Oriented Declarative Programming.
Comput. Lang., 1995

Memory disambiguation for general-purpose applications.
Proceedings of the 1995 Conference of the Centre for Advanced Studies on Collaborative Research, 1995

1993
The design of a multiparadigm programming language: I.
Microprocess. Microprogramming, 1993


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