Steven Wallace

According to our database1, Steven Wallace authored at least 18 papers between 1994 and 2016.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2016
A Research Framework for Business Sustainability using Information Exchange - A Firm Centric Perspective.
Proceedings of the 22nd Americas Conference on Information Systems, 2016

2013
Structural Stability and Virtual Team Conflict.
Proceedings of the 46th Hawaii International Conference on System Sciences, 2013

2012
Understanding Emergent Processes within New Product Development Teams.
Proceedings of the 18th Americas Conference on Information Systems, 2012

2011
Developing product innovation using Web 2.0: A field study.
Proceedings of the A Renaissance of Information Technology for Sustainability and Global Competitiveness. 17th Americas Conference on Information Systems, 2011

Structural Stability and Virtual Team Performance.
Proceedings of the A Renaissance of Information Technology for Sustainability and Global Competitiveness. 17th Americas Conference on Information Systems, 2011

2007
SuperPin: Parallelizing Dynamic Instrumentation for Real-Time Performance.
Proceedings of the Fifth International Symposium on Code Generation and Optimization (CGO 2007), 2007

2005
Pin: building customized program analysis tools with dynamic instrumentation.
Proceedings of the ACM SIGPLAN 2005 Conference on Programming Language Design and Implementation, 2005

2003
The rationale of the current optical networking initiatives.
Future Generation Comp. Syst., 2003

2002
Asim: A Performance Model Framework.
IEEE Computer, 2002

1999
Instruction Recycling on a Multiple-Path Processor.
Proceedings of the Fifth International Symposium on High-Performance Computer Architecture, 1999

1998
Modeled and Measured Instruction Fetching Performance for Superscalar Microprocessors.
IEEE Trans. Parallel Distrib. Syst., 1998

A scalable register file architecture for superscalar processors.
Microprocessors and Microsystems - Embedded Hardware Design, 1998

Threaded Multiple Path Execution.
Proceedings of the 25th Annual International Symposium on Computer Architecture, 1998

1997
Multiple Branch and Block Prediction.
Proceedings of the 3rd IEEE Symposium on High-Performance Computer Architecture (HPCA '97), 1997

1996
Instruction Fetching Mechanisms for Superscalar Microprocessors.
Proceedings of the Euro-Par '96 Parallel Processing, 1996

A scalable register file architecture for dynamically scheduled processors.
Proceedings of the Fifth International Conference on Parallel Architectures and Compilation Techniques, 1996

1995
Design and implementation of a 100 MHz centralized instruction window for a superscalar microprocessor.
Proceedings of the 1995 International Conference on Computer Design (ICCD '95), 1995

1994
Performance Issues of a Superscalar Microprocessor.
Proceedings of the 1994 International Conference on Parallel Processing, 1994


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