Chih-Chiang Hsu

According to our database1, Chih-Chiang Hsu authored at least 9 papers between 2004 and 2012.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2012
A 55nm 0.5V 128Kb cross-point 8T SRAM with data-aware dynamic supply Write-assist.
Proceedings of the IEEE 25th International SOC Conference, 2012

High-performance 0.6V VMIN 55nm 1.0Mb 6T SRAM with adaptive BL bleeder.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

2011
Online scheduling of workflow applications in grid environments.
Future Generation Comp. Syst., 2011

A high-performance low VMIN 55nm 512Kb disturb-free 8T SRAM with adaptive VVSS control.
Proceedings of the IEEE 24th International SoC Conference, SOCC 2011, Taipei, Taiwan, 2011

2010
ReBISR: A Reconfigurable Built-In Self-Repair Scheme for Random Access Memories in SOCs.
IEEE Trans. VLSI Syst., 2010

Online Scheduling of Workflow Applications in Grid Environment.
Proceedings of the Advances in Grid and Pervasive Computing, 5th International Conference, 2010

2008
A Low-Cost Programmable Memory BIST Design for Multiple Memory Instances.
Proceedings of the 2008 IEEE International Test Conference, 2008

2006
A Reconfigurable Built-In Self-Repair Scheme for Multiple Repairable RAMs in SOCs.
Proceedings of the 2006 IEEE International Test Conference, 2006

2004
Efficient Test Methodologies for Conditional Sum Adders.
Proceedings of the 13th Asian Test Symposium (ATS 2004), 2004


  Loading...