Geng-Cing Lin

According to our database1, Geng-Cing Lin authored at least 6 papers between 2011 and 2012.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2012
An all-digital Read Stability and Write Margin characterization scheme for CMOS 6T SRAM array.
Proceedings of Technical Program of 2012 VLSI Design, Automation and Test, 2012

A 55nm 0.55v 6T SRAM with variation-tolerant dual-tracking word-line under-drive and data-aware write-assist.
Proceedings of the International Symposium on Low Power Electronics and Design, 2012

High-performance 0.6V VMIN 55nm 1.0Mb 6T SRAM with adaptive BL bleeder.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

An all-digital bit transistor characterization scheme for CMOS 6T SRAM array.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

Design and implementation of dynamic Word-Line pulse write margin monitor for SRAM.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2012

2011
A high-performance low VMIN 55nm 512Kb disturb-free 8T SRAM with adaptive VVSS control.
Proceedings of the IEEE 24th International SoC Conference, SOCC 2011, Taipei, Taiwan, 2011


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