Wei-Chiang Shih
According to our database1,
Wei-Chiang Shih
authored at least 11 papers
between 2011 and 2021.
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Bibliography
2021
A Local Computing Cell and 6T SRAM-Based Computing-in-Memory Macro With 8-b MAC Operation for Edge AI Chips.
IEEE J. Solid State Circuits, 2021
2020
15.5 A 28nm 64Kb 6T SRAM Computing-in-Memory Macro with 8b MAC Operation for AI Edge Chips.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020
2013
A 40nm 1.0Mb pipeline 6T SRAM with variation-tolerant Step-Up Word-Line and Adaptive Data-Aware Write-Assist.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013
2012
A Single-Ended Disturb-Free 9T Subthreshold SRAM With Cross-Point Data-Aware Write Word-Line Structure, Negative Bit-Line, and Adaptive Read Operation Timing Tracing.
IEEE J. Solid State Circuits, 2012
Embedded SRAM ring oscillator for in-situ measurement of NBTI and PBTI degradation in CMOS 6T SRAM array.
Proceedings of Technical Program of 2012 VLSI Design, Automation and Test, 2012
An all-digital Read Stability and Write Margin characterization scheme for CMOS 6T SRAM array.
Proceedings of Technical Program of 2012 VLSI Design, Automation and Test, 2012
Proceedings of the IEEE 25th International SOC Conference, 2012
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2012
2011
A high-performance low VMIN 55nm 512Kb disturb-free 8T SRAM with adaptive VVSS control.
Proceedings of the IEEE 24th International SoC Conference, SOCC 2011, Taipei, Taiwan, 2011