Chin-Lung Su

According to our database1, Chin-Lung Su authored at least 12 papers between 2003 and 2015.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2015
Testing methods for quaternary content addressable memory using charge-sharing sensing scheme.
Proceedings of the 2015 IEEE International Test Conference, 2015

2013
Generalization of an Enhanced ECC Methodology for Low Power PSRAM.
IEEE Trans. Computers, 2013

2011
A Built-in Self-Diagnosis and Repair Design With Fail Pattern Identification for Memories.
IEEE Trans. Very Large Scale Integr. Syst., 2011

2010
Diagnosis of MRAM Write Disturbance Fault.
IEEE Trans. Very Large Scale Integr. Syst., 2010

2008
Write Disturbance Modeling and Testing for MRAM.
IEEE Trans. Very Large Scale Integr. Syst., 2008

Test and Diagnosis Algorithm Generation and Evaluation for MRAM Write Disturbance Fault.
Proceedings of the 17th IEEE Asian Test Symposium, 2008

2007
Diagnosis for MRAM write disturbance fault.
Proceedings of the 2007 IEEE International Test Conference, 2007

2006
Testing MRAM for Write Disturbance Fault.
Proceedings of the 2006 IEEE International Test Conference, 2006

2005
An Integrated ECC and Redundancy Repair Scheme for Memory Reliability Enhancement.
Proceedings of the 20th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2005), 2005

2004
MRAM Defect Analysis and Fault Modeli.
Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

Fail Pattern Identification for Memory Built-In Self-Repair.
Proceedings of the 13th Asian Test Symposium (ATS 2004), 2004

2003
A Processor-Based Built-In Self-Repair Design for Embedded Memories.
Proceedings of the 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, 2003


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