Chao-Hsun Chen

According to our database, Chao-Hsun Chen authored at least 13 papers between 2005 and 2022.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of five.

2022

Aging Impact of Power MOSFETs in Charger with Different Operation Frequency.

Kuan-Hsun Duh, Cheng-Wen Wu, Ming-Der Shieh, Chao-Hsun Chen, Ming-Yan Fan

Proceedings of the IEEE 31st Asian Test Symposium, 2022

Battery Pack Reliability and Endurance Enhancement for Electric Vehicles by Dynamic Reconfiguration.

Yu-You Chou, Cheng-Wen Wu, Ming-Der Shieh, Chao-Hsun Chen

Proceedings of the IEEE 31st Asian Test Symposium, 2022

2015

A hybrid built-in self-test scheme for DRAMs.

Chi-Chun Yang, Jin-Fu Li, Yun-Chao Yu, Kuan-Te Wu, Chih-Yen Lo, Chao-Hsun Chen, Jenn-Shiang Lai, Ding-Ming Kwai, Yung-Fa Chou

Proceedings of the VLSI Design, Automation and Test, 2015

2014

BIST-Assisted Tuning Scheme for Minimizing IO-Channel Power of TSV-Based 3D DRAMs.

Yun-Chao You, Chi-Chun Yang, Jin-Fu Li, Chih-Yen Lo, Chao-Hsun Chen, Jenn-Shiang Lai, Ding-Ming Kwai, Yung-Fa Chou, Cheng-Wen Wu

Proceedings of the 23rd IEEE Asian Test Symposium, 2014

2013

Generalization of an Enhanced ECC Methodology for Low Power PSRAM.

Po-Yuan Chen, Chin-Lung Su, Chao-Hsun Chen, Cheng-Wen Wu

IEEE Trans. Computers, 2013

2010

Built-In Self-Repair Schemes for Flash Memories.

Yu-Ying Hsiao, Chao-Hsun Chen, Cheng-Wen Wu

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

Economic Analysis of the HOY Wireless Test Methodology.

Yu-Tsao Hsing, Li-Ming Denq, Chao-Hsun Chen, Cheng-Wen Wu

IEEE Des. Test Comput., 2010

2008

A Systematic Approach to Memory Test Time Reduction.

Jen-Chieh Yeh, Chao-Hsun Chen, Cheng-Wen Wu, Shuo-Fen Kuo

IEEE Des. Test Comput., 2008

2007

Economic Aspects of Memory Built-in Self-Repair.

Rei-Fu Huang, Chao-Hsun Chen, Cheng-Wen Wu

IEEE Des. Test Comput., 2007

2006

A Built-In Self-Repair Scheme for NOR-Type Flash Memory.

Yu-Ying Hsiao, Chao-Hsun Chen, Cheng-Wen Wu

Proceedings of the 24th IEEE VLSI Test Symposium (VTS 2006), 30 April, 2006

An Enhanced EDAC Methodology for Low Power PSRAM.

Po-Yuan Chen, Yi-Ting Yeh, Chao-Hsun Chen, Jen-Chieh Yeh, Cheng-Wen Wu, Jeng-Shen Lee, Yu-Chang Lin

Proceedings of the 2006 IEEE International Test Conference, 2006

2005

A systematic approach to reducing semiconductor memory test time in mass production.

Jen-Chieh Yeh, Shyr-Fen Kuo, Cheng-Wen Wu, Chih-Tsun Huang, Chao-Hsun Chen

Proceedings of the 13th IEEE International Workshop on Memory Technology, 2005

Flash Memory Die Sort by a Sample Classification Method.

Yu-Chun Dawn, Jen-Chieh Yeh, Cheng-Wen Wu, Chia-Ching Wang, Yung-Chen Lin, Chao-Hsun Chen

Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005