Chia-Chun Lin

According to our database1, Chia-Chun Lin authored at least 33 papers between 2004 and 2020.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2020
LOOPLock: Logic Optimization-Based Cyclic Logic Locking.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

IMU-based Smart Knee Pad for Walking Distance and Stride Count Measurement.
Proceedings of the 21st International Symposium on Quality Electronic Design, 2020

Rehabilitation System for Limbs using IMUs.
Proceedings of the 21st International Symposium on Quality Electronic Design, 2020

A Convolutional Result Sharing Approach for Binarized Neural Network Inference.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

2019
Threshold Function Identification by Redundancy Removal and Comprehensive Weight Assignments.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

Using Online User-Generated Reviews to Predict Offline Box-Office Sales and Online DVD Store Sales in the O2O Era.
J. Theor. Appl. Electron. Commer. Res., 2019

A Glitch Key-Gate for Logic Locking.
Proceedings of the 32nd IEEE International System-on-Chip Conference, 2019

A Smart Single-Sensor Device for Instantaneously Monitoring Lower Limb Exercises.
Proceedings of the 32nd IEEE International System-on-Chip Conference, 2019

2018
On Synthesizing Memristor-Based Logic Circuits With Minimal Operational Pulses.
IEEE Trans. Very Large Scale Integr. Syst., 2018

Using range-equivalent circuits for facilitating bounded sequential equivalence checking.
Proceedings of the 2018 International Symposium on VLSI Design, 2018

Logic optimization with considering boolean relations.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

Efficient synthesis of approximate threshold logic circuits with an error rate guarantee.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

2017
An Efficient Indexing Method for Skyline Computations with Partially Ordered Domains.
IEEE Trans. Knowl. Data Eng., 2017

An efficient approach to finding potential products continuously.
Inf. Syst., 2017

In&Out: Restructuring for threshold logic network optimization.
Proceedings of the 18th International Symposium on Quality Electronic Design, 2017

2016
Traffic Anomalous Region Detection Model.
Proceedings of the 5th IIAI International Congress on Advanced Applied Informatics, 2016

2015
PAQCS: Physical Design-Aware Fault-Tolerant Quantum Circuit Synthesis.
IEEE Trans. Very Large Scale Integr. Syst., 2015

An adaptive reversible steganographic scheme based on the just noticeable distortion.
Multim. Tools Appl., 2015

2014
FTQLS: Fault-Tolerant Quantum Logic Synthesis.
IEEE Trans. Very Large Scale Integr. Syst., 2014

RMDDS: Reed-muller decision diagram synthesis of reversible logic circuits.
ACM J. Emerg. Technol. Comput. Syst., 2014

QLib: Quantum module library.
ACM J. Emerg. Technol. Comput. Syst., 2014

Rewiring for threshold logic circuit minimization.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

2013
Optimized Quantum Gate Library for Various Physical Machine Descriptions.
IEEE Trans. Very Large Scale Integr. Syst., 2013

2012
A novel multi-group exploiting modification direction method based on switch map.
Signal Process., 2012

Transformation for adults in an Internet-based learning environment - is it necessary to be self-directed?
Br. J. Educ. Technol., 2012

Design of Quantum Circuits for Random Walk Algorithms.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2012

Strong Tamper-Localization, Visual Secret Sharing Scheme Based on Exploiting Modification Direction.
Proceedings of the Seventh Asia Joint Conference on Information Security, 2012

2011
A mutual information based approach for evaluating the quality of clustering.
Proceedings of the IEEE International Conference on Acoustics, 2011

2008
A Hardware-Efficient H.264/AVC Motion-Estimation Design for High-Definition Video.
IEEE Trans. Circuits Syst. I Regul. Pap., 2008

A 242mW 10mm<sup>2</sup> 1080p H.264/AVC High-Profile Encoder Chip.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

2007
PMRME: A Parallel Multi-Resolution Motion Estimation Algorithm and Architecture for HDTV Sized H.264 Video Coding.
Proceedings of the IEEE International Conference on Acoustics, 2007

2006
A Fast Algorithm and Its Architecture for Motion Estimation in MPEG-4 AVC/H.264 Video Coding.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006

2004
Window Adaptive TCP for EGPRS Networks.
J. Inf. Sci. Eng., 2004


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