Cristiano Calligaro

According to our database1, Cristiano Calligaro authored at least 15 papers between 1996 and 2022.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2022
Analysis of Single Event Transient Effects in Standard Delay Cells Based on Decoupling Capacitors.
J. Circuits Syst. Comput., December, 2022

On the SCA Resistance of Crypto IP Cores.
Proceedings of the 23rd IEEE Latin American Test Symposium, 2022

2019
Recipes to build-up a rad-hard CMOS memory.
Proceedings of the 25th IEEE International Symposium on On-Line Testing and Robust System Design, 2019

Scalable and Configurable Multi-Chip SRAM in a Package for Space Applications.
Proceedings of the 2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2019

2016
Design of resistive non-volatile memories for rad-hard applications.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Re-usable 180nm CMOS dosimeter based on a floating gate device.
Proceedings of the 2016 IEEE International Conference on Electronics, Circuits and Systems, 2016

An integrated rad-hard test-vehicle for embedded emerging memories.
Proceedings of the 2016 IEEE International Conference on Electronics, Circuits and Systems, 2016

A 400 Mbps radiation hardened by design LVDS compliant driver and receiver.
Proceedings of the 2016 IEEE International Conference on Electronics, Circuits and Systems, 2016

2015
A subthreshold, low-power, RHBD reference circuit, for earth observation and communication satellites.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

2014
Radiation-hardened techniques for CMOS flash ADC.
Proceedings of the 21st IEEE International Conference on Electronics, Circuits and Systems, 2014

2013
Non volatile memory for FPGA booting in space.
Proceedings of the 2013 NASA/ESA Conference on Adaptive Hardware and Systems, 2013

2012
SkyFlash EC project: Architecture for a 1Mbit S-Flash for space applications.
Proceedings of the 19th IEEE International Conference on Electronics, Circuits and Systems, 2012

2009
A radiation hardened 512 kbit SRAM in 180 nm CMOS technology.
Proceedings of the 16th IEEE International Conference on Electronics, 2009

2008
Design of a rad-hard library of digital cells for space applications.
Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008

1996
Technological and design constraints for multilevel flash memories.
Proceedings of Third International Conference on Electronics, Circuits, and Systems, 1996


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