Alberto Stabile

Orcid: 0000-0002-6868-8329

According to our database1, Alberto Stabile authored at least 20 papers between 2008 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2023
Modelling and Verification of MOS Transistors at Cryogenic Temperature.
Proceedings of the 12th International Conference on Modern Circuits and Systems Technologies, 2023


2022
The AM08 Associative Memory ASIC Design, Architecture and Evaluation methodology.
Proceedings of the 11th International Conference on Modern Circuits and Systems Technologies, 2022

2018
A very compact population count circuit for associative memories.
Proceedings of the 7th International Conference on Modern Circuits and Systems Technologies, 2018

Characterization of an LVDS Link in 28 nm CMOS for Multi-Purpose Pattern Recognition.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Design and Characterization of New Content Addressable Memory Cells.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018


2017
Design of LVDS driver and receiver in 28 nm CMOS technology for Associative Memories.
Proceedings of the 6th International Conference on Modern Circuits and Systems Technologies, 2017

Heterogeneous computing system platform for high-performance pattern recognition applications.
Proceedings of the 6th International Conference on Modern Circuits and Systems Technologies, 2017

Power Distribution Network optimization for Associative Memories.
Proceedings of the 6th International Conference on Modern Circuits and Systems Technologies, 2017

Population count circuits for Associative Memories: A comparison study.
Proceedings of the 6th International Conference on Modern Circuits and Systems Technologies, 2017

A low-power and high-density Associative Memory in 28 nm CMOS technology.
Proceedings of the 6th International Conference on Modern Circuits and Systems Technologies, 2017

2015

Double-redundant design methodology to improve radiation hardness in pixel detector readout ICs.
Proceedings of the 2015 IEEE International Conference on Electronics, 2015


2014
Radiation-tolerant standard cell synthesis using double-rail redundant approach.
Proceedings of the 21st IEEE International Conference on Electronics, Circuits and Systems, 2014

Characterisation of an Associative Memory Chip for high-energy physics experiments.
Proceedings of the IEEE International Instrumentation and Measurement Technology Conference, 2014

2012
A new XOR-based Content Addressable Memory architecture.
Proceedings of the 19th IEEE International Conference on Electronics, Circuits and Systems, 2012

2009
A radiation hardened 512 kbit SRAM in 180 nm CMOS technology.
Proceedings of the 16th IEEE International Conference on Electronics, 2009

2008
Design of a rad-hard library of digital cells for space applications.
Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008


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