Marko S. Andjelkovic

Orcid: 0000-0001-6419-2062

According to our database1, Marko S. Andjelkovic authored at least 38 papers between 2015 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2023
Towards Reconfigurable CNN Accelerator for FPGA Implementation.
IEEE Trans. Circuits Syst. II Express Briefs, March, 2023

Adaptive Lock-Step System for Resilient Multiprocessing Architectures.
Proceedings of the IEEE Nordic Circuits and Systems Conference, 2023


Towards a Comprehensive SET Analysis Flow for VLSI Circuits using Static Timing Analysis.
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2023

A Machine Learning-driven EDAC Method for Space-Application Memory.
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2023

SET and SEU Hardened Clock Gating Cell.
Proceedings of the 38th Conference on Design of Circuits and Integrated Systems, 2023

2022
Response of Commercial P-Channel Power VDMOS Transistors to Ionizing Irradiation and Bias Temperature Stress.
J. Circuits Syst. Comput., December, 2022

Analysis of Single Event Transient Effects in Standard Delay Cells Based on Decoupling Capacitors.
J. Circuits Syst. Comput., December, 2022

A design concept for radiation hardened RADFET readout system for space applications.
Microprocess. Microsystems, April, 2022

A methodology for characterization, modeling and mitigation of single event transient effects in CMOS standard combinational cells (Eine Methode zur Charakterisierung, Modellierung und Minderung von SET Effekten in kombinierten CMOS-Standardzellen)
PhD thesis, 2022

Solar Particle Event and Single Event Upset Prediction from SRAM-Based Monitor and Supervised Machine Learning.
IEEE Trans. Emerg. Top. Comput., 2022

Fast Error Propagation Probability Estimates by Answer Set Programming and Approximate Model Counting.
IEEE Access, 2022

2021
Design and Evaluation of Radiation-Hardened Standard Cell Flip-Flops.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021

Monitoring of Particle Flux and LET Variations with Pulse Stretching Inverters.
CoRR, 2021

Reliability Analysis in Less than 200 Lines of Code.
Proceedings of the 12th IEEE Latin America Symposium on Circuits and System, 2021

A Tunable Single Event Transient Filter Based on Digitally Controlled Capacitive Delay Cells.
Proceedings of the 36th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2021

2020
Double cell upsets mitigation through triple modular redundancy.
Microelectron. J., 2020

PISA: Power-robust Multiprocessor Design for Space Applications.
Proceedings of the 26th IEEE International Symposium on On-Line Testing and Robust System Design, 2020

Characterization of Single Event Transient Effects in Standard Delay Cells.
Proceedings of the 27th IEEE International Conference on Electronics, Circuits and Systems, 2020

A Review of Particle Detectors for Space-Borne Self-Adaptive Fault-Tolerant Systems.
Proceedings of the IEEE East-West Design & Test Symposium, 2020

Design Concept for Radiation-Hardening of Triple Modular Redundancy TSPC Flip-Flops.
Proceedings of the 23rd Euromicro Conference on Digital System Design, 2020

Design of Radiation Hardened RADFET Readout System for Space Applications.
Proceedings of the 23rd Euromicro Conference on Digital System Design, 2020

Hardware Accelerator Design with Supervised Machine Learning for Solar Particle Event Prediction.
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2020

2019
Characterization and Modeling of SET Generation Effects in CMOS Standard Logic Cells.
Proceedings of the 25th IEEE International Symposium on On-Line Testing and Robust System Design, 2019

A Particle Detector Based on Pulse Stretching Inverter Chain.
Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019

Design of SRAM-Based Low-Cost SEU Monitor for Self-Adaptive Multiprocessing Systems.
Proceedings of the 22nd Euromicro Conference on Digital System Design, 2019

2018
Study of the operation and SET robustness of a CMOS pulse stretching circuit.
Microelectron. Reliab., 2018

Use of Decoupling Cells for Mitigation of SET Effects in CMOS Combinational Gates.
Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018

Impact of Resistive Open and Bridge Defects on the SET Robustness of Standard CMOS Combinational Logic.
Proceedings of the 2018 IEEE East-West Design & Test Symposium, 2018

D-SET Mitigation Using Common Clock Tree Insertion Techniques for Triple-Clock TMR Flip-Flop.
Proceedings of the 21st Euromicro Conference on Digital System Design, 2018

Flip-Flop SEUs Mitigation through Partial Hardening of Internal Latch and Adjustment of Clock Duty Cycle.
Proceedings of the 21st IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2018

2017
Assessment of the amplitude-duration criterion for SET/SEU robustness evaluation.
Proceedings of the 23rd IEEE International Symposium on On-Line Testing and Robust System Design, 2017

Design of an On-chip System for the SET Pulse Width Measurement.
Proceedings of the Euromicro Conference on Digital System Design, 2017

An analysis of the operation and SET robustness of a CMOS pulse stretching circuit.
Proceedings of the 20th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2017

A Critical Charge Model for Estimating the SET and SEU Sensitivity: A Muller C-Element Case Study.
Proceedings of the 26th IEEE Asian Test Symposium, 2017

2016
SET response of a SEL protection switch for 130 and 250 nm CMOS technologies.
Proceedings of the 22nd IEEE International Symposium on On-Line Testing and Robust System Design, 2016

2015
Circuit-Level Simulation of the Single Event Transients in an On-Chip Single Event Latchup Protection Switch.
J. Electron. Test., 2015

Simulation-Based Analysis of the Single Event Transient Response of a Single Event Latchup Protection Switch.
Proceedings of the 18th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2015


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