Georgios Tzimpragos

Orcid: 0000-0002-0127-4703

According to our database1, Georgios Tzimpragos authored at least 21 papers between 2013 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

Online presence:

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Bibliography

2024
Quantum Circuit Simulation with Fast Tensor Decision Diagram.
CoRR, 2024

2022
Computing with Temporal Operators
PhD thesis, 2022

Low-Cost Superconducting Fan-Out with Repurposed Josephson Junctions.
CoRR, 2022

Pulsar: A Superconducting Delay-Line Memory.
CoRR, 2022

PyLSE: a pulse-transfer level language for superconductor electronics.
Proceedings of the PLDI '22: 43rd ACM SIGPLAN International Conference on Programming Language Design and Implementation, San Diego, CA, USA, June 13, 2022

2021
Temporal Computing With Superconductors.
IEEE Micro, 2021

In-sensor classification with boosted race trees.
Commun. ACM, 2021

Superconducting Computing with Alternating Logic Elements.
Proceedings of the 48th ACM/IEEE Annual International Symposium on Computer Architecture, 2021

TiAcc: Triangle-inequality based Hardware Accelerator for K-means on FPGAs.
Proceedings of the 21st IEEE/ACM International Symposium on Cluster, 2021

2020
Agile Hardware Development and Instrumentation With PyRTL.
IEEE Micro, 2020

Language Support for Navigating Architecture Design in Closed Form.
ACM J. Emerg. Technol. Comput. Syst., 2020

A Computational Temporal Logic for Superconducting Accelerators.
Proceedings of the ASPLOS '20: Architectural Support for Programming Languages and Operating Systems, 2020

2019
Boosted Race Trees for Low Energy Classification.
Proceedings of the Twenty-Fourth International Conference on Architectural Support for Programming Languages and Operating Systems, 2019

2018
Charm: A Language for Closed-Form High-Level Architecture Modeling.
Proceedings of the 45th ACM/IEEE Annual International Symposium on Computer Architecture, 2018

2017
A pythonic approach for rapid hardware prototyping and instrumentation.
Proceedings of the 27th International Conference on Field Programmable Logic and Applications, 2017

2016
A Survey on FEC Codes for 100 G and Beyond Optical Networks.
IEEE Commun. Surv. Tutorials, 2016

Application debug in FPGAs in the presence of multiple asynchronous clocks.
Proceedings of the 2016 International Conference on Field-Programmable Technology, 2016

2014
A Low-Latency Algorithm and FPGA Design for the Min-Search of LDPC Decoders.
Proceedings of the 2014 IEEE International Parallel & Distributed Processing Symposium Workshops, 2014

Flexible FEC codes for next-generation software-defined optical transceivers.
Proceedings of the 16th International Conference on Transparent Optical Networks, 2014

2013
Automatic implementation of low-complexity QC-LDPC encoders.
Proceedings of the 2013 23rd International Workshop on Power and Timing Modeling, 2013

A low-complexity implementation of QC-LDPC encoder in reconfigurable logic.
Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013


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